公开(公告)号：US20220285844A1

公开(公告)日：2022-09-08

申请号：US17190521

申请日：2021-03-03

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Sadia Naseem ,  Meysam Moallem

IPC: H01Q9/04 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

Abstract: An antenna apparatus in a packaged electronic device includes: an antenna assembly with a conductive antenna, and an insulator; a conductive feed line extending on or in a substrate; a conductive layer with an aperture on or in the substrate between the conductive feed line and an exposed portion of the conductive antenna; and a support structure mounted to a portion of the substrate and to a portion of the antenna assembly to support the antenna assembly and to provide an air gap between the exposed portion of the conductive antenna and the aperture.

公开(公告)号：US11062982B2

公开(公告)日：2021-07-13

申请号：US16681221

申请日：2019-11-12

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

公开(公告)号：US10366944B2

公开(公告)日：2019-07-30

申请号：US15973828

申请日：2018-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

公开(公告)号：US10186478B2

公开(公告)日：2019-01-22

申请号：US15842608

申请日：2017-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

公开(公告)号：US11791168B2

公开(公告)日：2023-10-17

申请号：US17172043

申请日：2021-02-09

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4821 ,  H01L23/49582

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US11018111B2

公开(公告)日：2021-05-25

申请号：US16423104

申请日：2019-05-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  James Huckabee ,  Vikas Gupta

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H01L21/304 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.

公开(公告)号：US20210116407A1

公开(公告)日：2021-04-22

申请号：US17137251

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: G01N27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.

公开(公告)号：US10916448B2

公开(公告)日：2021-02-09

申请号：US16027558

申请日：2018-07-05

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L23/495 ,  H01L21/48

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US20200321677A1

公开(公告)日：2020-10-08

申请号：US16716642

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Hassan Omar Ali ,  Juan Alejandro Herbsommer ,  Benjamin Stassen Cook ,  Vikas Gupta ,  Athena Lin ,  Swaminathan Sankaran

IPC: H01P3/16 ,  H01P3/12 ,  H01Q1/22 ,  H04B1/40

Abstract: A device includes a multilayer substrate having a first surface and a second surface opposite the first surface. An integrated circuit is mounted on the second surface of the multilayer substrate, the integrated circuit having transmission circuitry configured to process millimeter wave signals. A substrate waveguide having a substantially solid wall is formed within a portion of the multilayer substrate perpendicular to the first surface. The substrate waveguide has a first end with the wall having an edge exposed on the first surface of the multilayer substrate. A reflector is located in one of the layers of the substrate and is coupled to an edge of the wall on an opposite end of the substrate waveguide.

公开(公告)号：US10784188B2

公开(公告)日：2020-09-22

申请号：US16443653

申请日：2019-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.