公开(公告)号：US12255077B2

公开(公告)日：2025-03-18

申请号：US18488990

申请日：2023-10-17

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta

IPC: H01L23/495 ,  H01L21/48

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

公开(公告)号：US11437333B2

公开(公告)日：2022-09-06

申请号：US15840497

申请日：2017-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device includes a lead frame and a semiconductor device. A solder joint is coupled between the lead frame and a terminal on the semiconductor device. A reflow wall is on a portion of the lead frame and is in contact with the solder joint. A molding compound covers portions of the semiconductor device, the lead frame, the solder joint, and the reflow wall.

公开(公告)号：US10883953B2

公开(公告)日：2021-01-05

申请号：US16162011

申请日：2018-10-16

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: G01N27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.

公开(公告)号：US10559524B1

公开(公告)日：2020-02-11

申请号：US16133117

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L21/00 ,  H01L29/00 ,  H01L23/12 ,  H01L23/495 ,  H01L23/64 ,  H01L23/00 ,  H01L21/56 ,  H01F27/28

Abstract: A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.

公开(公告)号：US20190157195A1

公开(公告)日：2019-05-23

申请号：US16252412

申请日：2019-01-18

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495 ,  H01L23/31

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

公开(公告)号：US10083896B1

公开(公告)日：2018-09-25

申请号：US15470486

申请日：2017-03-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L21/50 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

公开(公告)号：US20180190577A1

公开(公告)日：2018-07-05

申请号：US15842608

申请日：2017-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vikas Gupta ,  Daniel Yong Lin

IPC: H01L23/495

CPC classification number: H01L23/49579 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/80815

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

公开(公告)号：US09780060B2

公开(公告)日：2017-10-03

申请号：US15368413

申请日：2016-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Lin ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L24/29 ,  H01L21/304 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/544 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29034 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

公开(公告)号：US11677152B2

公开(公告)日：2023-06-13

申请号：US17190521

申请日：2021-03-03

Applicant: Texas Instruments Incorporated

Inventor： Vikas Gupta ,  Sadia Naseem ,  Meysam Moallem

IPC: H01Q9/04 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01Q9/0407 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6677 ,  H01L2224/81815

Abstract: An antenna apparatus in a packaged electronic device includes: an antenna assembly with a conductive antenna, and an insulator; a conductive feed line extending on or in a substrate; a conductive layer with an aperture on or in the substrate between the conductive feed line and an exposed portion of the conductive antenna; and a support structure mounted to a portion of the substrate and to a portion of the antenna assembly to support the antenna assembly and to provide an air gap between the exposed portion of the conductive antenna and the aperture.

公开(公告)号：US11598742B2

公开(公告)日：2023-03-07

申请号：US17137251

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: H01L21/768 ,  G01N27/22 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.