公开(公告)号：US09978441B2

公开(公告)日：2018-05-22

申请号：US15445230

申请日：2017-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika Tanaka ,  Keiji Ikeda ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/565 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/10873

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.