公开(公告)号：US10714629B2

公开(公告)日：2020-07-14

申请号：US16122834

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Nobuyoshi Saito ,  Tomomasa Ueda ,  Kentaro Miura ,  Keiji Ikeda ,  Tsutomu Tezuka

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02

Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.

公开(公告)号：US10950735B2

公开(公告)日：2021-03-16

申请号：US16351245

申请日：2019-03-12

Applicant: Toshiba Memory Corporation

Inventor： Junji Kataoka ,  Tomomasa Ueda ,  Tomoaki Sawabe ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L45/00 ,  H01L29/24

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.

公开(公告)号：US10790396B2

公开(公告)日：2020-09-29

申请号：US16103880

申请日：2018-08-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Tomomasa Ueda ,  Keiji Ikeda ,  Tsutomu Tezuka ,  Nobuyoshi Saito

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/108 ,  H01L29/778 ,  H01L21/44 ,  H01L21/4763

Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.

公开(公告)号：US20180269217A1

公开(公告)日：2018-09-20

申请号：US15698077

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Kentaro MIURA ,  Tomomasa Ueda ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L27/11524 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/11524 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/786

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

公开(公告)号：US09978441B2

公开(公告)日：2018-05-22

申请号：US15445230

申请日：2017-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika Tanaka ,  Keiji Ikeda ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C7/02 ,  G11C11/4091 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/565 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/10873

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.

公开(公告)号：US09786683B1

公开(公告)日：2017-10-10

申请号：US15271407

申请日：2016-09-21

Applicant: Toshiba Memory Corporation

Inventor： Kiwamu Sakuma ,  Keiji Ikeda ,  Masumi Saitoh

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/24 ,  H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/0847 ,  H01L29/42376

Abstract: This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

公开(公告)号：US11024719B2

公开(公告)日：2021-06-01

申请号：US16563307

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoaki Sawabe ,  Nobuyoshi Saito ,  Junji Kataoka ,  Tomomasa Ueda ,  Keiji Ikeda

IPC: H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L27/24 ,  H01L29/78

Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.

公开(公告)号：US10553601B2

公开(公告)日：2020-02-04

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura ,  Tomoaki Sawabe

IPC: H01L27/11568 ,  G11C16/04 ,  H01L29/66 ,  G11C5/06 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L29/792

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US20180268893A1

公开(公告)日：2018-09-20

申请号：US15916427

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/406 ,  G11C11/403 ,  G11C11/4094

CPC classification number: G11C11/40607 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2245

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

公开(公告)号：US10056150B2

公开(公告)日：2018-08-21

申请号：US15452178

申请日：2017-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/34 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C5/025 ,  G11C11/005 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.