公开(公告)号：US20200066868A1

公开(公告)日：2020-02-27

申请号：US16670375

申请日：2019-10-31

Applicant: Toshiba Memory Corporation

Inventor： Tsunehiro INO ,  Yusuke Higashi ,  Toshinori Numata ,  Yuuichi Kamimuta

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.

公开(公告)号：US20180268893A1

公开(公告)日：2018-09-20

申请号：US15916427

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/406 ,  G11C11/403 ,  G11C11/4094

CPC classification number: G11C11/40607 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4094 ,  G11C2207/2245

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

公开(公告)号：US10056150B2

公开(公告)日：2018-08-21

申请号：US15452178

申请日：2017-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/34 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C5/025 ,  G11C11/005 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.

公开(公告)号：US10510862B2

公开(公告)日：2019-12-17

申请号：US16134314

申请日：2018-09-18

Applicant: Toshiba Memory Corporation

Inventor： Tsunehiro Ino ,  Yusuke Higashi ,  Toshinori Numata ,  Yuuichi Kamimuta

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/49 ,  H01L27/11587

Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.

公开(公告)号：US10367054B2

公开(公告)日：2019-07-30

申请号：US15699300

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hidenori Miyagawa ,  Riichiro Takaishi ,  Toshinori Numata

IPC: H01L29/04 ,  H01L27/11582 ,  H01L29/36 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.

公开(公告)号：US10332581B2

公开(公告)日：2019-06-25

申请号：US15916427

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/403 ,  G11C11/408

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

公开(公告)号：US20180082750A1

公开(公告)日：2018-03-22

申请号：US15452178

申请日：2017-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji IKEDA ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C16/24 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C5/025 ,  G11C11/005 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.

公开(公告)号：US20180082733A1

公开(公告)日：2018-03-22

申请号：US15445230

申请日：2017-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Keiji Ikeda ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/4091 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/565 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/10873

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.

公开(公告)号：US09806082B2

公开(公告)日：2017-10-31

申请号：US15266798

申请日：2016-09-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika Tanaka ,  Keiji Ikeda ,  Yoshihiro Ueda ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/24 ,  H01L27/108 ,  G11C11/4091 ,  H01L29/24 ,  H01L29/78 ,  G11C11/408 ,  H01L27/06 ,  G11C11/404 ,  G11C11/405

CPC classification number: H01L27/10897 ,  G11C5/025 ,  G11C11/404 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/1082 ,  H01L29/24 ,  H01L29/7827

Abstract: According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.

公开(公告)号：US20190296122A1

公开(公告)日：2019-09-26

申请号：US16134314

申请日：2018-09-18

Applicant: Toshiba Memory Corporation

Inventor： Tsunehiro INO ,  Yusuke Higashi ,  Toshinori Numata ,  Yuuichi Kamimuta

IPC: H01L29/51 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.