公开(公告)号：US5673045A

公开(公告)日：1997-09-30

申请号：US429794

申请日：1995-04-27

申请人： Koichi Sato ,  Kazuhiro Tsuji

发明人： Koichi Sato ,  Kazuhiro Tsuji

IPC分类号： H03M1/46 ,  H03M1/68 ,  H03M1/76

CPC分类号： H03M1/685 ,  H03M1/765

摘要： A digital-to-analog conversion circuit includes a first reference voltage generation circuit for generating a plurality of first reference voltages, a plurality of second reference voltage generation circuits for generating a plurality of second reference voltages created by dividing a difference in potential between adjacent two of the first reference voltages, a first selective control circuit for, upon receiving a first digital input signal group, selecting one of the first reference voltages and applying the selected one to a specified one of a plurality of signal lines during a first period, and selecting all of second reference voltages generated in one of the plurality of second reference voltage generation circuits and applying all the selected second reference voltages to signal lines other than the specified signal line, respectively, during a second period succeeding the first period, and a second selective control circuit for, upon receiving a second digital input signal group, applying a voltage of the specified signal line to an analog output terminal during the first period, and applying voltages of the signal lines other than the specified signal line to the analog output terminal during the second period.

摘要翻译： 数模转换电路包括用于产生多个第一参考电压的第一参考电压产生电路，用于产生多个第二参考电压的多个第二参考电压产生电路，所述多个第二参考电压通过将相邻两个电压之间的电位差除以 第一选择控制电路，用于在接收到第一数字输入信号组时，在第一时段期间选择第一参考电压之一并将所选择的一个应用于多个信号线中的指定的一个;以及 选择在所述多个第二参考电压产生电路之一中产生的所有第二参考电压，并且在所述第一周期之后的第二周期期间分别将所选择的所述第二参考电压分别施加到除所述指定信号线之外的信号线，以及第二参考电压 选择控制电路，用于在接收到第二数字输入信号gr时 在第一时段期间，将指定信号线的电压施加到模拟输出端，并且在第二周期期间将除指定信号线之外的信号线的电压施加到模拟输出端。

公开(公告)号：US5285115A

公开(公告)日：1994-02-08

申请号：US827648

申请日：1992-01-29

申请人： Kazuhiro Tsuji

发明人： Kazuhiro Tsuji

IPC分类号： G01R19/00 ,  G01R19/165 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03M1/34 ,  H03K5/153 ,  G11C7/06

CPC分类号： H03K3/35613 ,  H03K5/249

摘要： A comparator device comprising a offset-compensating comparator and a positive-feedback comparator. A reference voltage and an input voltage are applied to the input terminals of the offset-compensating comparator. The non-inverting and inverting output terminals of the offset-compensating comparator are connected to the inverting and non-inverting input terminals of the positive-feedback comparator, respectively. The positive-feedback comparator starts comparing the input voltage with the reference voltage before the offset-compensating comparator finishes comparing the input voltage with the reference voltage. Hence, the comparator device operates at high speed and has a great gain. In addition, the offset voltage can be reduced. A transistor is connected between the differential input terminals of the positive-feedback comparator, for setting both differential input terminals at the same potential at the time the comparator starts comparing the input voltage with the reference voltage. Therefore, the differential inputs to the positive-feedback comparator have no noise.

摘要翻译： 一种比较器装置，包括偏移补偿比较器和正反馈比较器。 参考电压和输入电压被施加到偏移补偿比较器的输入端子。 偏移补偿比较器的同相和反相输出端分别连接到正反馈比较器的反相和非反相输入端。 正反馈比较器在偏移补偿比较器完成将输入电压与参考电压进行比较之前开始将输入电压与参考电压进行比较。 因此，比较器装置以高速运转并具有很大的增益。 此外，可以减小偏移电压。 晶体管连接在正反馈比较器的差分输入端子之间，用于在比较器开始将输入电压与参考电压进行比较时将两个差分输入端子设置为相同的电位。 因此，正反馈比较器的差分输入没有噪声。

公开(公告)号：US5057838A

公开(公告)日：1991-10-15

申请号：US526904

申请日：1990-05-22

申请人： Kazuhiro Tsuji ,  Tetsuya Iida ,  Takayuki Satoh

发明人： Kazuhiro Tsuji ,  Tetsuya Iida ,  Takayuki Satoh

IPC分类号： H03M1/74 ,  H03M1/06 ,  H03M1/68 ,  H03M1/76

CPC分类号： H03M1/0651 ,  H03M1/685 ,  H03M1/765

摘要： A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

公开(公告)号：US4816613A

公开(公告)日：1989-03-28

申请号：US137323

申请日：1987-12-23

申请人： Katsuo Ito ,  Kazunori Kinoshita ,  Kazuhiro Tsuji

发明人： Katsuo Ito ,  Kazunori Kinoshita ,  Kazuhiro Tsuji

IPC分类号： H05K5/04 ,  H05K5/02 ,  H05K9/00

CPC分类号： H05K9/006 ,  Y10S174/34 ,  Y10S174/35

摘要： An electrical shielding case for shielding a plurality of circuits from each other, which includes a plurality of plate portions formed by dividing a metallic flat plate, and remaining parts of the plate portions left for connection when outer peripheries of the plate portions are cut off, with each of the plate portions being folded at the remaining portions as fulcrums so as to form the electrical shielding case, and is characterized in that there are provided bendable cut and raised portions formed at parts of other confronting plate portions interfering with end faces of the plate portions upon folding thereof.

摘要翻译： 用于屏蔽多个电路的电屏蔽壳体，其包括通过划分金属平板而形成的多个板部分，以及当板部分的外周缘被切断时剩下的用于连接的板部分， 其中每个板部分在剩余部分处作为支点折叠以形成电屏蔽壳体，其特征在于，在其它相对的板部分的部分处形成弯曲的切割和凸起部分，该部分干涉其的端面 折叠时的板部分。