公开(公告)号：US20100199901A1

公开(公告)日：2010-08-12

申请号：US12668930

申请日：2008-07-30

Applicant: Tae-Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

Inventor： Tae-Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

IPC: D05C17/00 ,  D07B1/06 ,  D02G3/02

CPC classification number: D02G3/12 ,  A41D27/00 ,  D02G3/28 ,  D02G3/441 ,  D05C7/06 ,  D10B2331/04 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029

Abstract: The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.

Abstract translation: 本发明涉及可应用于智能纺织品的导电金属复合刺绣线及其使用的绣花电路。 更具体地，本发明涉及可用作电源和信号传输线的智能纺织品的导电金属复合刺绣线和绣花电路。 本发明提供了一种由金属复合刺绣纱线和电介质织物基材组成的绣花线路，其中将导电金属复合刺绣纱线绣在电介质织物基底上以形成电路。

公开(公告)号：US20050243614A1

公开(公告)日：2005-11-03

申请号：US11178561

申请日：2005-07-12

Applicant: Tae-Jin Kang ,  Bong-Hwa Jeong

Inventor： Tae-Jin Kang ,  Bong-Hwa Jeong

IPC: G11C5/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract translation: 用于输出存储在半导体存储器件的核心中的数据的数据输出电路包括用于通过使用外部时钟产生上升时钟和下降时钟的时钟发生器，用于输出上升时钟和下降时钟的时钟转发器 响应于外部电压电平检查信号的高压时钟和低电压时钟;电平移位器，用于输出通过移位与高电压时钟同步的数据产生的高电压数据;数据载体，用于输出低电压数据 与低电压时钟同步;以及数据中继器，用于响应于外部电压电平检查信号输出高电压数据和低电压数据中的一个。