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25 条记录 (耗时 0.019 秒)

    Method and pattern for reducing interconnect failures
    11.
    发明授权
    Method and pattern for reducing interconnect failures 有权
    减少互连故障的方法和模式

    公开(公告)号：US06831365B1

    公开(公告)日：2004-12-14

    申请号：US10448656

    申请日：2003-05-30

    申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

    发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

    IPC分类号： H01L2348

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

    摘要翻译： 描述了用于减少互连故障的方法和模式。 该方法和图案用于金属/电介质/金属的多层结构。 至少一个辅助图案附着到多层结构的一个金属层。 由辅助图案产生的热应力梯度可以收集金属层的空位，以防止应力诱导的空隙在连接两个金属层的通孔塞的底部产生。

    Structure for reducing stress-induced voiding in an interconnect of integrated circuits
    12.
    发明申请
    Structure for reducing stress-induced voiding in an interconnect of integrated circuits 审中-公开
    用于减少集成电路互连中应力引起的空隙的结构

    公开(公告)号：US20060108696A1

    公开(公告)日：2006-05-25

    申请号：US11328614

    申请日：2006-01-10

    申请人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

    发明人： Chih-Hsiang Yao ,  Chin-Chiu Hsia ,  Wen-Kai Wan

    IPC分类号： H01L23/48

    CPC分类号： H01L23/528 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

    摘要翻译： 一种用于减小集成电路的互连中的应力引起的空隙的结构，所述互连具有第一部分和至少第二部分比第一部分更窄的部分。 该结构包括设置在第一部分中的靠近第一部分和第二部分的相交处的至少一个内部狭槽。 本发明还包括制造互连和结构的方法。 导电互连结构包括第一部分和比第一部分更窄的至少第二部分; 以及包括形成在所述第一部分和所述第二部分的交叉点处的过渡部分的应力减小结构。

    SHALLOW TRENCH ISOLATION DUMMY PATTERN AND LAYOUT METHOD USING THE SAME
    14.
    发明申请
    SHALLOW TRENCH ISOLATION DUMMY PATTERN AND LAYOUT METHOD USING THE SAME 有权
    使用相同的浅层分离分离模式和布局方法

    公开(公告)号：US20080209381A1

    公开(公告)日：2008-08-28

    申请号：US12116284

    申请日：2008-05-07

    申请人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    发明人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

    摘要翻译： 用于浅沟槽隔离（STI）的虚拟单元格图案。 活动和浅沟槽隔离区域由周长界定。 有源区域图案与有源区域完全重叠，并且浅沟槽隔离区域中的第一多晶硅图案在有源区域图案之外。 还公开了使用该方法的布局方法。

    Method for forming an interconnection structure for ic metallization
    15.
    发明授权
    Method for forming an interconnection structure for ic metallization 有权
    用于形成用于ic金属化的互连结构的方法

    公开(公告)号：US07291557B2

    公开(公告)日：2007-11-06

    申请号：US10940147

    申请日：2004-09-13

    申请人： Wen-Kai Wan ,  Chin-Chiu Hsia

    发明人： Wen-Kai Wan ,  Chin-Chiu Hsia

    IPC分类号： H01L21/44

    CPC分类号： H01L21/7684

    摘要： A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectric layer. A conductive layer is deposited on the barrier layer and filling the opening. Then, a step of planarization is performed to form the interconnection structure, such that a peripheral edge of a top surface of the interconnection structure is no lower than a top surface of the barrier layer.

    摘要翻译： 在集成电路中形成互连结构的方法包括以下步骤。 在半导体衬底上形成电介质层。 在电介质层上形成开口。 在开口和电介质层的内壁上形成阻挡层。 导电层沉积在阻挡层上并填充开口。 然后，进行平面化的工序，形成互连结构，使得互连结构的上表面的周缘不低于势垒层的顶面。

    Scheme to define laser fuse in dual damascene CU process
    16.
    发明授权
    Scheme to define laser fuse in dual damascene CU process 失效
    激光熔丝在双镶嵌CU工艺中的定义

    公开(公告)号：US06737345B1

    公开(公告)日：2004-05-18

    申请号：US10238290

    申请日：2002-09-10

    申请人： Kang-Cheng Lin ,  Chin-Chiu Hsia

    发明人： Kang-Cheng Lin ,  Chin-Chiu Hsia

    IPC分类号： H01L2144

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.

    摘要翻译： 为了激光烧蚀的目的，用于半导体集成电路器件的半导体集成电路器件的方法在部分蚀刻双镶嵌集成方案中，在顶部通孔开口处限定薄铜熔丝，从而有效地降低可熔连接中的顶部金属厚度。 该方法的一些优点是：（a）避免铜熔丝与低介电材料接触，这受到激光烧蚀的热冲击，（b）使用更好的厚度控制增加保险丝上的绝缘材料厚度，最重要的是（ c）降低铜熔丝厚度，便于铜熔丝的激光烧蚀，最后，（d）使用USG，未掺杂的硅酸盐玻璃避免与低介电常数材料的直接接触。

    Stripe board dummy metal for reducing coupling capacitance
    18.
    发明授权
    Stripe board dummy metal for reducing coupling capacitance 有权
    用于减少耦合电容的条形板虚拟金属

    公开(公告)号：US07312486B1

    公开(公告)日：2007-12-25

    申请号：US10189910

    申请日：2002-07-05

    申请人： Kang-Cheng Lin ,  Chin-Chiu Hsia

    发明人： Kang-Cheng Lin ,  Chin-Chiu Hsia

    IPC分类号： H01L29/80

    CPC分类号： H01L23/5222 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.

    摘要翻译： 已知在嵌入金属的分布不均匀的介电层的CMP的CMP之后，已经发现了抛光。 这个问题已经通过填充嵌入金属的密度低的区域来解决，其中未连接的区域代替均匀填充有金属，由金属图案组成，其中给定区域内的组合面积为 区域本身。 这种图案的两个示例是线条纹图案（类似于镶木地板瓦片）和棋盘图案。 提供的数据比较了使用这种类型的图案相对于常规固体图案产生的寄生电容。 还讨论了对准这些区域以减小其与布线通道重叠程度的效果。

    Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same
    19.
    发明申请
    Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same 有权
    浅沟槽隔离模式和使用它的布局方法

    公开(公告)号：US20100252907A1

    公开(公告)日：2010-10-07

    申请号：US12818033

    申请日：2010-06-17

    申请人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    发明人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    IPC分类号： H01L23/544

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

    摘要翻译： 用于浅沟槽隔离（STI）的虚拟单元格图案。 活动和浅沟槽隔离区域由周长界定。 有源区域图案与有源区域完全重叠，并且浅沟槽隔离区域中的第一多晶硅图案在有源区域图案之外。 还公开了使用该方法的布局方法。

    Shallow trench isolation dummy pattern and layout method using the same
    20.
    发明申请
    Shallow trench isolation dummy pattern and layout method using the same 有权
    浅沟隔离虚拟图案和布局方法使用相同

    公开(公告)号：US20050112840A1

    公开(公告)日：2005-05-26

    申请号：US10993937

    申请日：2004-11-19

    申请人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    发明人： Kelvin Yih-Yuh Doong ,  Chin-Chiu Hsia

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.

    摘要翻译： 用于浅沟槽隔离（STI）的虚拟单元格图案。 活动和浅沟槽隔离区域由周长界定。 有源区域图案与有源区域完全重叠，并且浅沟槽隔离区域中的第一多晶硅图案在有源区域图案之外。 还公开了使用该方法的布局方法。