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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    13.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20160336429A1

    公开(公告)日：2016-11-17

    申请号：US14714227

    申请日：2015-05-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-Yi PENG ,  Chih Chieh YEH ,  Chih-Sheng CHANG ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

    Abstract translation: 半导体器件包括设置在衬底上的鳍结构; 设置在所述鳍结构的一部分上的栅极结构; 源/漏结构，其包括未被栅极结构覆盖的鳍结构的一部分; 形成在鳍状结构上的层间电介质层，栅极结构和源极/漏极结构; 形成在所述层间电介质层中的接触孔; 以及设置在接触孔中的接触材料。 翅片结构在第一方向上延伸并且包括上层，其中上层的一部分从隔离绝缘层暴露。 栅极结构在垂直于第一方向的第二方向上延伸。 接触材料包括磷化硅层和金属层。

    PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES
    14.
    发明申请
    PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210280486A1

    公开(公告)日：2021-09-09

    申请号：US16807305

    申请日：2020-03-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Yi PENG ,  Ching-Hua LEE ,  Song-Bor LEE

    IPC: H01L23/31 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions

    CORE-SHELL NANOSTRUCTURES FOR SEMICONDUCTOR DEVICES
    15.
    发明申请
    CORE-SHELL NANOSTRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210273050A1

    公开(公告)日：2021-09-02

    申请号：US16806597

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Yi PENG ,  Song-Bor LEE

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/04 ,  H01L29/423

    Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

    SEMICONDUCTOR TEST DEVICE AND MANUFACTURING METHOD THEREOF
    16.
    发明申请
    SEMICONDUCTOR TEST DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210018544A1

    公开(公告)日：2021-01-21

    申请号：US16984073

    申请日：2020-08-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-Yi PENG ,  Chia-Cheng HO ,  Ming-Shiang LIN ,  Chih-Sheng CHANG ,  Carlos H. DIAZ

    IPC: G01R27/16 ,  H01L21/66

    Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

    FINFET FABRICATION METHODS
    20.
    发明申请
    FINFET FABRICATION METHODS 审中-公开

    公开(公告)号：US20200066869A1

    公开(公告)日：2020-02-27

    申请号：US16673661

    申请日：2019-11-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. More

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

    Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

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