公开(公告)号：US11410991B2

公开(公告)日：2022-08-09

申请号：US17155268

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US11145713B2

公开(公告)日：2021-10-12

申请号：US16601998

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H03K19/0185 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US11139290B2

公开(公告)日：2021-10-05

申请号：US16534259

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu

IPC: H01L27/06 ,  H01L29/778 ,  H01L25/07 ,  H01L29/66 ,  H01L21/761

Abstract: The present disclosure relates to a semiconductor device including a first high electron mobility transistor (HEMT) device disposed within a semiconductor structure and having a first source, a first drain, and a first gate; a second HEMT device disposed within the semiconductor structure and having a second source, a second drain, and a second gate, the second source coupled to the first drain; and a diode-connected transistor device disposed within the semiconductor structure and comprising a third source, a third gate, and a third drain, the third drain coupled to the second gate.

公开(公告)号：US20210159334A1

公开(公告)日：2021-05-27

申请号：US17142618

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun Lin Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US10923467B2

公开(公告)日：2021-02-16

申请号：US16584773

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06 ,  H01L23/522

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US10854711B2

公开(公告)日：2020-12-01

申请号：US16683604

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Wei Yao ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Man-Ho Kwan

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761 ,  H01L27/06 ,  H01L27/085 ,  H01L29/10 ,  H01L21/8252 ,  H01L21/8234

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a channel layer disposed over a substrate and including a first material. An active layer is over the channel layer and includes a second material different than the first material. An isolation structure has a horizontally extending segment that is below the channel layer and one or more vertically extending segments that are directly over the horizontally extending segment. One or more contacts extend through the channel layer and the active layer to contact the one or more vertically extending segments.

公开(公告)号：US20200044014A1

公开(公告)日：2020-02-06

申请号：US16601998

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H03K19/0185 ,  H01L27/088

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20200043912A1

公开(公告)日：2020-02-06

申请号：US16584795

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06

Abstract: Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.

公开(公告)号：US20200027874A1

公开(公告)日：2020-01-23

申请号：US16584773

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L29/06

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

公开(公告)号：US10483259B2

公开(公告)日：2019-11-19

申请号：US15942728

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Yi-Min Chen ,  Chih-Yuan Chan

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/40 ,  H01L23/522

Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.