公开(公告)号：US11664431B2

公开(公告)日：2023-05-30

申请号：US17144671

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/41758 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/7786

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

公开(公告)号：US20210273065A1

公开(公告)日：2021-09-02

申请号：US16862875

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

公开(公告)号：US20210265241A1

公开(公告)日：2021-08-26

申请号：US16936654

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

公开(公告)号：US20220223699A1

公开(公告)日：2022-07-14

申请号：US17144671

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

公开(公告)号：US20160111501A1

公开(公告)日：2016-04-21

申请号：US14516696

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Chen ,  Jiun-Lei Jerry Yu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  King-Yuen Wong

IPC: H01L29/205 ,  H01L29/423 ,  H03K17/687 ,  H01L23/31 ,  H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/205 ,  H01L23/3171 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract translation: 提供了采用用于隔离和/或限定有源区域的新颖布局的III-V族晶体管器件。 III-V族异质结组置于衬底之上或之内，内部漏电极设置在III-V族异质结上。 栅极具有环形并且布置在围绕内部漏电极的III-V族异质结上。 外源电极具有围绕栅极的III-V族异质结布置的环状区域。 还提供了用于制造III-V族晶体管器件的方法。

公开(公告)号：US11521915B2

公开(公告)日：2022-12-06

申请号：US16936654

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

公开(公告)号：US11145713B2

公开(公告)日：2021-10-12

申请号：US16601998

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H03K19/0185 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20200044014A1

公开(公告)日：2020-02-06

申请号：US16601998

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H03K19/0185 ,  H01L27/088

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20190096988A1

公开(公告)日：2019-03-28

申请号：US15964636

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US09397168B2

公开(公告)日：2016-07-19

申请号：US14516696

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Chen ,  Jiun-Lei Jerry Yu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  King-Yuen Wong

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L23/31 ,  H01L29/778 ,  H03K17/687

CPC classification number: H01L29/205 ,  H01L23/3171 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract translation: 提供了采用用于隔离和/或限定有源区域的新颖布局的III-V族晶体管器件。 III-V族异质结组置于衬底之上或之内，内部漏电极设置在III-V族异质结上。 栅极具有环形并且布置在围绕内部漏电极的III-V族异质结上。 外源电极具有围绕栅极的III-V族异质结布置的环状区域。 还提供了用于制造III-V族晶体管器件的方法。