公开(公告)号：US09711463B2

公开(公告)日：2017-07-18

申请号：US14596326

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC: H01L21/00 ,  H01L23/00 ,  H01L29/00 ,  H01L29/20 ,  H01L29/78 ,  H01L23/58 ,  H01L23/522 ,  H01L21/784

CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.

公开(公告)号：US11195945B2

公开(公告)日：2021-12-07

申请号：US16558518

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu ,  Liang-Yu Su ,  Yun-Hsiang Wang

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/47 ,  H01L29/417

Abstract: In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

公开(公告)号：US20180026029A1

公开(公告)日：2018-01-25

申请号：US15215651

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Syuan Lin ,  Ming-Cheng Lin ,  King-Yuen Wong ,  Jiun-Lei Yu ,  Chun Lin Tsai

IPC: H01L27/02 ,  H01L49/02 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L28/20 ,  H01L27/0248 ,  H01L27/0605

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.

公开(公告)号：US20210066483A1

公开(公告)日：2021-03-04

申请号：US16558518

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu ,  Liang-Yu Su ,  Yun-Hsiang Wang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/47 ,  H01L21/285 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

公开(公告)号：US10083921B2

公开(公告)日：2018-09-25

申请号：US15631392

申请日：2017-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC: H01L29/00 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

公开(公告)号：US11139290B2

公开(公告)日：2021-10-05

申请号：US16534259

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu

IPC: H01L27/06 ,  H01L29/778 ,  H01L25/07 ,  H01L29/66 ,  H01L21/761

Abstract: The present disclosure relates to a semiconductor device including a first high electron mobility transistor (HEMT) device disposed within a semiconductor structure and having a first source, a first drain, and a first gate; a second HEMT device disposed within the semiconductor structure and having a second source, a second drain, and a second gate, the second source coupled to the first drain; and a diode-connected transistor device disposed within the semiconductor structure and comprising a third source, a third gate, and a third drain, the third drain coupled to the second gate.

公开(公告)号：US20170294391A1

公开(公告)日：2017-10-12

申请号：US15631392

申请日：2017-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC: H01L23/58 ,  H01L29/778 ,  H01L29/40 ,  H01L21/78 ,  H01L29/20

CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

公开(公告)号：US20160204074A1

公开(公告)日：2016-07-14

申请号：US14596326

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Syuan Lin ,  Jiun-Lei Jerry Yu ,  Ming-Cheng Lin ,  Hsin-Chieh Huang ,  Chao-Hsiung Wang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L21/784 ,  H01L23/5226 ,  H01L23/562 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.

Abstract translation: 一些实施例涉及切割半导体晶片的方法。 该半导体晶片包括在器件层内形成的器件结构。 器件层布置在器件层的上表面内。 形成裂缝停止件，其围绕装置结构并加强半导体晶片以防止切割期间的开裂。 使用激光器沿着裂纹停止点外的划线形成凹槽。 凹槽完全延伸穿过器件层并进入半导体晶片的上表面区域。 然后用切割刀沿着带槽划线切割半导体晶片，将半导体晶片分成两个或更多个管芯。 通过将槽完全延伸穿过器件层，该方法避免了由刀片锯引起的对器件层的损坏，从而避免了器件结构的相关性能下降。