公开(公告)号：US11152250B2

公开(公告)日：2021-10-19

申请号：US16912533

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US10699940B2

公开(公告)日：2020-06-30

申请号：US15963297

申请日：2018-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/70 ,  H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US10658372B2

公开(公告)日：2020-05-19

申请号：US16578792

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wei Yin ,  Shu-Yuan Ku ,  Chun-Fai Cheng

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/40 ,  H01L27/088

Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.

公开(公告)号：US10424588B2

公开(公告)日：2019-09-24

申请号：US15808618

申请日：2017-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wei Yin ,  Shu-Yuan Ku ,  Chun-Fai Cheng

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/40 ,  H01L27/088

Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.

公开(公告)号：US20190139969A1

公开(公告)日：2019-05-09

申请号：US15808618

申请日：2017-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Wei Yin ,  Shu-Yuan Ku ,  Chun-Fai Cheng

IPC: H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.