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    Gate Dielectric Preserving Gate Cut Process
    1.
    发明申请
    Gate Dielectric Preserving Gate Cut Process 审中-公开

    公开(公告)号：US20190157135A1

    公开(公告)日：2019-05-23

    申请号：US15963297

    申请日：2018-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

    IPC: H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78

    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

    Gate structures for semiconductor devices
    2.
    发明授权
    Gate structures for semiconductor devices 有权

    公开(公告)号：US12218013B2

    公开(公告)日：2025-02-04

    申请号：US18388419

    申请日：2023-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Fai Cheng ,  Chang-Miao Liu ,  Kuan-Chung Chen

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer

    Gate Dielectric Preserving Gate Cut Process
    3.
    发明申请
    Gate Dielectric Preserving Gate Cut Process 有权

    公开(公告)号：US20220037196A1

    公开(公告)日：2022-02-03

    申请号：US17501818

    申请日：2021-10-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

    IPC: H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28

    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

    Gate structures for semiconductor devices
    4.
    发明授权
    Gate structures for semiconductor devices 有权

    公开(公告)号：US11107736B1

    公开(公告)日：2021-08-31

    申请号：US16835987

    申请日：2020-03-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Fai Cheng ,  Chang-Miao Liu ,  Kuan-Chung Chen

    IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L21/3115

    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.

    Gate dielectric preserving gate cut process
    7.
    发明授权
    Gate dielectric preserving gate cut process 有权

    公开(公告)号：US11145536B2

    公开(公告)日：2021-10-12

    申请号：US16709291

    申请日：2019-12-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

    IPC: H01L21/70 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66

    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

    Gate Dielectric Preserving Gate Cut Process
    8.
    发明申请
    Gate Dielectric Preserving Gate Cut Process 审中-公开

    公开(公告)号：US20200328106A1

    公开(公告)日：2020-10-15

    申请号：US16912533

    申请日：2020-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

    IPC: H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

    Cutting Metal Gates in Fin Field Effect Transistors
    9.
    发明申请
    Cutting Metal Gates in Fin Field Effect Transistors 审中-公开

    公开(公告)号：US20200279854A1

    公开(公告)日：2020-09-03

    申请号：US16876525

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Wei Yin ,  Shu-Yuan Ku ,  Chun-Fai Cheng

    IPC: H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

    Abstract: A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.

    Cutting Metal Gates in Fin Field Effect Transistors
    10.
    发明申请
    Cutting Metal Gates in Fin Field Effect Transistors 审中-公开

    公开(公告)号：US20200020701A1

    公开(公告)日：2020-01-16

    申请号：US16578792

    申请日：2019-09-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Wei Yin ,  Shu-Yuan Ku ,  Chun-Fai Cheng

    IPC: H01L27/11 ,  H01L21/8234 ,  H01L29/66

    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.

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