公开(公告)号：US10461171B2

公开(公告)日：2019-10-29

申请号：US15965183

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Chih-Chang Hung ,  I-Wei Yang ,  Chih-Ming Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure includes forming a first dummy gate stack and a second dummy gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first dummy gate stack and the second dummy gate stack. The method includes removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer and removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench in the dielectric layer. The method includes partially removing the first metal gate stack, the second metal gate stack, and the dielectric layer to form a recess. The method includes forming an insulating structure to partially or completely fill the recess.

公开(公告)号：US09666461B1

公开(公告)日：2017-05-30

申请号：US15016275

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yii-Cheng Lin ,  Chih-Ming Sun ,  Pinyen Lin

IPC: H01L21/67 ,  H01L21/306 ,  B08B9/08

CPC classification number: H01L21/67161 ,  B08B9/08 ,  H01L21/30604 ,  H01L21/67063 ,  H01L21/6719 ,  H01L21/67207

Abstract: A semiconductor processing device includes a first etching chamber, a second etching chamber, and an etching module. The etching module is adapted to interchangeably contain the first etching chamber or the second etching chamber for wafer etching. A semiconductor process using the semiconductor processing device is also provided.

公开(公告)号：US11876013B2

公开(公告)日：2024-01-16

申请号：US17501818

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76232 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/4011 ,  H01L29/785 ,  H01L21/823437 ,  H01L29/66795

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US11145536B2

公开(公告)日：2021-10-12

申请号：US16709291

申请日：2019-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US20200328106A1

公开(公告)日：2020-10-15

申请号：US16912533

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US11152250B2

公开(公告)日：2021-10-19

申请号：US16912533

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US10699940B2

公开(公告)日：2020-06-30

申请号：US15963297

申请日：2018-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/70 ,  H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US20190157135A1

公开(公告)日：2019-05-23

申请号：US15963297

申请日：2018-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/762 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

公开(公告)号：US20170250098A1

公开(公告)日：2017-08-31

申请号：US15597100

申请日：2017-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yii-Cheng Lin ,  Chih-Ming Sun ,  Pinyen Lin

IPC: H01L21/67 ,  B08B9/08 ,  H01L21/306

CPC classification number: H01L21/67161 ,  B08B9/08 ,  H01L21/30604 ,  H01L21/67063 ,  H01L21/6719 ,  H01L21/67207

Abstract: A semiconductor processing device includes a first etching chamber, a second etching chamber, and an etching module. The etching module is adapted to interchangeably contain the first etching chamber or the second etching chamber for wafer etching. A semiconductor process using the semiconductor processing device is also provided.

公开(公告)号：US20220037196A1

公开(公告)日：2022-02-03

申请号：US17501818

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Yuan Ku ,  Chih-Ming Sun ,  Chun-Fai Cheng

IPC: H01L21/762 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.