公开(公告)号：US09448281B2

公开(公告)日：2016-09-20

申请号：US14134259

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。

公开(公告)号：US12073167B2

公开(公告)日：2024-08-27

申请号：US18163916

申请日：2023-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US11670672B2

公开(公告)日：2023-06-06

申请号：US17306796

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US11567105B2

公开(公告)日：2023-01-31

申请号：US17326147

申请日：2021-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

Abstract: A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.

公开(公告)号：US10886190B2

公开(公告)日：2021-01-05

申请号：US16681687

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh Yang ,  Yung-Chow Peng ,  Chung-Peng Hsieh ,  Sa-Lly Liu

IPC: H01L29/00 ,  H01L23/34 ,  H01L23/64 ,  H01L23/552 ,  H01L23/522 ,  H01L49/02

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20200227516A1

公开(公告)日：2020-07-16

申请号：US16834265

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L49/02 ,  H01L23/522

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US20190067150A1

公开(公告)日：2019-02-28

申请号：US15883462

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh Yang ,  Yung-Chow Peng ,  Chung-Peng Hsieh ,  Sa-Lly Liu

IPC: H01L23/34 ,  H01L23/552 ,  H01L23/64

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20150177327A1

公开(公告)日：2015-06-25

申请号：US14134259

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。

公开(公告)号：US10170414B2

公开(公告)日：2019-01-01

申请号：US15693083

申请日：2017-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11582

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US10161967B2

公开(公告)日：2018-12-25

申请号：US14991936

申请日：2016-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

IPC: G01R19/00 ,  G01R13/00 ,  G01R31/28 ,  G01R13/02 ,  G01R31/317

Abstract: A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.