公开(公告)号：US12033937B2

公开(公告)日：2024-07-09

申请号：US17099002

申请日：2020-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L23/5228 ,  H01L28/00 ,  H01L28/24 ,  H10B43/27

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US11681854B2

公开(公告)日：2023-06-20

申请号：US17703898

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953 ,  G06F30/373 ,  G06F119/06

CPC classification number: G06F30/398 ,  G06F30/367 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/373 ,  G06F2119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

公开(公告)号：US10510637B2

公开(公告)日：2019-12-17

申请号：US15883462

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh Yang ,  Yung-Chow Peng ,  Chung-Peng Hsieh ,  Sa-Lly Liu

IPC: H01L29/00 ,  H01L23/34 ,  H01L23/64 ,  H01L23/552 ,  H01L23/522 ,  H01L49/02

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US09773731B2

公开(公告)日：2017-09-26

申请号：US15009500

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US11308255B2

公开(公告)日：2022-04-19

申请号：US16886550

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953 ,  G06F30/373 ,  G06F119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

公开(公告)号：US11035886B2

公开(公告)日：2021-06-15

申请号：US16212090

申请日：2018-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.

公开(公告)号：US12032896B2

公开(公告)日：2024-07-09

申请号：US18312835

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/3953 ,  G06F119/06

CPC classification number: G06F30/398 ,  G06F30/367 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/373 ,  G06F2119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

公开(公告)号：US11835551B2

公开(公告)日：2023-12-05

申请号：US18069813

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

CPC classification number: G01R13/00 ,  G01R13/0218 ,  G01R31/2851 ,  G01R31/31726

Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

公开(公告)号：US11574104B2

公开(公告)日：2023-02-07

申请号：US17135565

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US10998397B2

公开(公告)日：2021-05-04

申请号：US16834265

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L49/02 ,  H01L23/522

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.