公开(公告)号：US09202916B2

公开(公告)日：2015-12-01

申请号：US14142396

申请日：2013-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yeh Huang ,  Kai-Hsiang Chang ,  Chih-Chen Jiang ,  Yi-Wei Peng ,  Kuan-Yu Lin ,  Ming-Shan Tsai ,  Ching-Lun Lai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract translation: 提供了用于形成半导体器件结构的实施例。 半导体器件结构包括形成在衬底上的衬底和栅叠层结构。 半导体器件结构还包括形成在栅极堆叠结构的侧壁上的栅极间隔物。 半导体器件结构还包括形成在衬底中的隔离结构和邻近隔离结构形成的源极/漏极应力结构。 源极/漏极应力器结构包括沿（311）和（111）晶体取向形成的覆盖层。

公开(公告)号：US20150177327A1

公开(公告)日：2015-06-25

申请号：US14134259

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。

公开(公告)号：US09871137B2

公开(公告)日：2018-01-16

申请号：US15332800

申请日：2016-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yeh Huang ,  Kai-Hsiang Chang ,  Chih-Chen Jiang ,  Yi-Wei Peng ,  Kuan-Yu Lin ,  Ming-Shan Tsai ,  Ching-Lun Lai

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/04 ,  H01L21/225 ,  H01L21/306 ,  H01L23/535 ,  H01L29/06 ,  H01L29/36 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.

公开(公告)号：US09478617B2

公开(公告)日：2016-10-25

申请号：US14927144

申请日：2015-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yeh Huang ,  Kai-Hsiang Chang ,  Chih-Chen Jiang ,  Yi-Wei Peng ,  Kuan-Yu Lin ,  Ming-Shan Tsai ,  Ching-Lun Lai

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/306 ,  H01L29/04 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract translation: 提供了形成半导体器件结构的方法。 该方法包括提供衬底并在衬底中形成隔离结构。 该方法还包括在衬底上形成栅极叠层结构，并蚀刻衬底的一部分以在衬底中形成凹陷，并且凹槽与栅堆叠结构相邻。 该方法包括在凹部中形成应力层，并且应力层的一部分沿（311）和（111）晶体取向生长。

公开(公告)号：US09448281B2

公开(公告)日：2016-09-20

申请号：US14134259

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。