公开(公告)号：US11769652B2

公开(公告)日：2023-09-26

申请号：US16525330

申请日：2019-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jr-Sheng Chen ,  An-Chi Li ,  Shih-Che Huang ,  Chih-Hsien Hsu ,  Zhi-Hao Huang ,  Ming Chih Wang ,  Yu-Pei Chiang ,  Chun Yan Chen

IPC: H01J37/32 ,  H01L21/67 ,  G06F30/00

CPC classification number: H01J37/32449 ,  G06F30/00 ,  H01J37/3211 ,  H01J2237/3341 ,  H01J2237/3343 ,  H01L21/67069

Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.

公开(公告)号：US10964547B2

公开(公告)日：2021-03-30

申请号：US16693389

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Han Meng ,  Chih-Hsien Hsu ,  Jr-Sheng Chen ,  An-Chi Li ,  Lin-Ching Huang ,  Yu-Pei Chiang

IPC: H01L21/3065 ,  B81C1/00 ,  H01L21/308 ,  H01L21/311

Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.

公开(公告)号：US10529578B2

公开(公告)日：2020-01-07

申请号：US16175750

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Han Meng ,  Chih-Hsien Hsu ,  Jr-Sheng Chen ,  An-Chi Li ,  Lin-Ching Huang ,  Yu-Pei Chiang

IPC: H01L21/3065 ,  B81C1/00 ,  H01L21/308 ,  H01L21/311

Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.