公开(公告)号：US20240096867A1

公开(公告)日：2024-03-21

申请号：US18526395

申请日：2023-12-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  G06F30/394 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

公开(公告)号：US20230387035A1

公开(公告)日：2023-11-30

申请号：US18232713

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-Cheng Lin

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4857 ,  H01L24/20 ,  H01L2224/214

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

公开(公告)号：US20230093380A1

公开(公告)日：2023-03-23

申请号：US18070303

申请日：2022-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/092 ,  G06F30/392

Abstract: A method includes placing, in a layout, a plurality of first cells each having a first NFET fin number. The first cells are swapped with a plurality of second cells each having a second NFET fin number less than the first NFET fin number. After swapping the first cells with the second cells, a timing critical path in the layout is identified. Some of the second cells in the identified timing critical path are swapped with a plurality of third cells each having a third NFET fin number greater than the second NFET fin number. After swapping some of the second cells in the identified timing critical path with the third cells, an integrated circuit is fabricated based on the layout.

公开(公告)号：US20220149033A1

公开(公告)日：2022-05-12

申请号：US17585402

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

IPC: H01L27/02 ,  H01L27/092

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US20190164883A1

公开(公告)日：2019-05-30

申请号：US16264622

申请日：2019-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L49/02 ,  H01L29/423 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively.

公开(公告)号：US20190123036A1

公开(公告)日：2019-04-25

申请号：US16216843

申请日：2018-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  G06F17/50 ,  H01L23/485

Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

公开(公告)号：US20250159998A1

公开(公告)日：2025-05-15

申请号：US19020097

申请日：2025-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Chung-Hsing WANG ,  Yi-Kan CHENG

IPC: H10D89/10 ,  G06F111/20 ,  H10D84/85

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US20240395819A1

公开(公告)日：2024-11-28

申请号：US18791008

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/092 ,  G06F30/392

Abstract: A method includes placing, in a layout, a plurality of first cells each having a first NFET fin number. The first cells are swapped with a plurality of second cells each having a second NFET fin number less than the first NFET fin number. After swapping the first cells with the second cells, a timing critical path in the layout is identified. Some of the second cells in the identified timing critical path are swapped with a plurality of third cells each having a third NFET fin number greater than the second NFET fin number. After swapping some of the second cells in the identified timing critical path with the third cells, an integrated circuit is fabricated based on the layout.

公开(公告)号：US20240387369A1

公开(公告)日：2024-11-21

申请号：US18789467

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

公开(公告)号：US20230187434A1

公开(公告)日：2023-06-15

申请号：US18167651

申请日：2023-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen YOUNG ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Jiann-Tyng TZENG ,  Shun-Li CHEN ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Chun-Kuang CHEN ,  Ru-Gun LIU

IPC: H01L27/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394

CPC classification number: H01L27/0207 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823425 ,  H01L21/823431 ,  H01L23/485 ,  G06F30/394 ,  H01L23/528

Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.