公开(公告)号：US20250070011A1

公开(公告)日：2025-02-27

申请号：US18401789

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

公开(公告)号：US12224325B2

公开(公告)日：2025-02-11

申请号：US18353027

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20240387658A1

公开(公告)日：2024-11-21

申请号：US18783869

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US20240347598A1

公开(公告)日：2024-10-17

申请号：US18750589

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L29/0649 ,  H01L29/785 ,  H01L23/528

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.

公开(公告)号：US20240339511A1

公开(公告)日：2024-10-10

申请号：US18746288

申请日：2024-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Cheng-Chi Chuang

IPC: H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/78696

Abstract: A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

公开(公告)号：US20240339406A1

公开(公告)日：2024-10-10

申请号：US18749812

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US20240250134A1

公开(公告)日：2024-07-25

申请号：US18313634

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Chun-Yuan Chen ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Kuo-Nan Yang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

公开(公告)号：US12021119B2

公开(公告)日：2024-06-25

申请号：US18358576

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L29/0649 ,  H01L29/785 ,  H01L23/528

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

公开(公告)号：US20240186179A1

公开(公告)日：2024-06-06

申请号：US18420209

申请日：2024-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/02603 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/5329 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US11862559B2

公开(公告)日：2024-01-02

申请号：US17337962

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate.