公开(公告)号：US20230061716A1

公开(公告)日：2023-03-02

申请号：US17707481

申请日：2022-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Kun Lai ,  Yi-Wen Wu ,  Kuo-Chin Chang ,  Po-Hao Tsai ,  Mirng-Ji Lii

IPC: H01L23/00

Abstract: Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

公开(公告)号：US11222859B2

公开(公告)日：2022-01-11

申请号：US16866828

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hao Hsu ,  Wei-Hsiang Tu ,  Kuo-Chin Chang ,  Mirng-Ji Lii

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.

公开(公告)号：US11145564B2

公开(公告)日：2021-10-12

申请号：US16395435

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

公开(公告)号：US11127704B2

公开(公告)日：2021-09-21

申请号：US16169753

申请日：2018-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Haw Tsao ,  Chen-Shien Chen ,  Cheng-Hung Tsai ,  Kuo-Chin Chang ,  Li-Huan Chu

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 μm.