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    INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS
    11.
    发明申请
    INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS 有权

    公开(公告)号：US20220149077A1

    公开(公告)日：2022-05-12

    申请号：US17586285

    申请日：2022-01-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

    Inventor： Tian-Yu XIE ,  Xin-Yong WANG ,  Lei PAN ,  Kuo-Ji CHEN

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

    Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

    DEVICE WITH ESD PROTECTION
    15.
    发明申请
    DEVICE WITH ESD PROTECTION 审中-公开

    公开(公告)号：US20190164952A1

    公开(公告)日：2019-05-30

    申请号：US16105494

    申请日：2018-08-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Heng CHANG ,  Kuo-Ji CHEN ,  Ming-Hsiang SONG

    IPC: H01L27/02

    Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.

    SINGLE-GATE-OXIDE POWER INVERTER AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    16.
    发明申请
    SINGLE-GATE-OXIDE POWER INVERTER AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 审中-公开

    公开(公告)号：US20190097420A1

    公开(公告)日：2019-03-28

    申请号：US16143315

    申请日：2018-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hung CHEN ,  Kuo-Ji CHEN ,  Shao-Yu CHOU

    IPC: H02H9/04 ,  H01L27/02 ,  H03K17/082

    Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

    FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD)
    17.
    发明申请
    FinFET AND TRANSISTORS WITH RESISTORS AND PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) 审中-公开
    具有电阻器和防止静电放电（ESD）的保护的FinFET和晶体管

    公开(公告)号：US20150294968A1

    公开(公告)日：2015-10-15

    申请号：US14746893

    申请日：2015-06-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Yi YANG ,  Kuo-Ji CHEN ,  Chien-Yuan LEE

    IPC: H01L27/02 ,  H01L29/78 ,  H01L49/02 ,  H01L27/06 ,  H01L23/528

    CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

    Abstract translation: FinFET器件包括形成在多电平互连半导体器件中的对应的多个鳍片上的多个FinFET器件。 每个源极和每个漏极通过位于最低互连电平以下的金属电阻元件耦合到金属互连电平。 在一个实施例中，在多个翅片上延伸的金属段包括到每个翅片的触点，从而提供不同长度的下面的金属电阻元件。 多个翅片和下面的金属段被布置成使得每个FinFET器件具有由源极和漏极金属电阻元件提供的相同的总电阻，即使与鳍片相关联的源极金属电阻元件和漏极金属电阻元件可具有 不同长度 该布置为每个FinFET器件提供相同的导通电阻和相同的ESD故障电流。

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