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    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM 有权

    公开(公告)号：US20210272984A1

    公开(公告)日：2021-09-02

    申请号：US17024351

    申请日：2020-09-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chien Yao HUANG ,  Wun-Jie LIN ,  Kuo-Ji CHEN

    IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  G06F30/392

    Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

    DEVICE INCLUDING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION COMPONENT
    6.
    发明申请
    DEVICE INCLUDING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION COMPONENT 有权

    公开(公告)号：US20230123887A1

    公开(公告)日：2023-04-20

    申请号：US18066060

    申请日：2022-12-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Heng CHANG ,  Kuo-Ji CHEN ,  Ming-Hsiang SONG

    IPC: H01L27/02 ,  H01L27/088

    Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM 有权

    公开(公告)号：US20220037365A1

    公开(公告)日：2022-02-03

    申请号：US16940930

    申请日：2020-07-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chien Yao HUANG ,  Wun-Jie LIN ,  Kuo-Ji CHEN

    IPC: H01L27/118 ,  G06F30/392 ,  H01L21/8238 ,  H01L27/02

    Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.

    METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION
    8.
    发明申请
    METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION 审中-公开
    在标准电池配置中用金属化电阻形成集成电路的方法和装置

    公开(公告)号：US20150249080A1

    公开(公告)日：2015-09-03

    申请号：US14714369

    申请日：2015-05-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei Yu MA ,  Bo-Ting CHEN ,  Ting Yu CHEN ,  Kuo-Ji CHEN ,  Li-Chun TIEN

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L27/06 ,  H01L27/118

    CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

    Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

    Abstract translation: 集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。 在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。 制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及 施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

    SYSTEM AND METHOD FOR ARBITRARY METAL SPACING FOR SELF-ALIGNED DOUBLE PATTERNING
    9.
    发明申请
    SYSTEM AND METHOD FOR ARBITRARY METAL SPACING FOR SELF-ALIGNED DOUBLE PATTERNING 有权
    用于自对准双模式的ARBITAL金属间距的系统和方法

    公开(公告)号：US20140264894A1

    公开(公告)日：2014-09-18

    申请号：US13888405

    申请日：2013-05-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Li-Chun TIEN ,  Chen-Chi WU ,  Kuo-Ji CHEN

    IPC: G06F17/50 ,  H01L21/033

    CPC classification number: G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0337 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.

    Abstract translation: 一种集成电路包括被配置为具有第一电压电位的器件的第一导电结构，该器件的第二导电结构被配置为具有不同于第一电压电位的第二电压电位，以及设置在并分离之间的维持和平结构 第一导电结构和第二导电结构。 维持和平结构与第一导电结构和第二导电结构中的至少一个分离，形成用于自对准双图案化（“SADP”）工艺的导线的固定间隔距离。

    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES
    10.
    发明公开
    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES 审中-公开

    公开(公告)号：US20240321781A1

    公开(公告)日：2024-09-26

    申请号：US18731021

    申请日：2024-05-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tao-Yi HUNG ,  Wun-Jie LIN ,  Jam-Wem LEE ,  Kuo-Ji CHEN

    IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

    CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

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