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    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM 有权

    公开(公告)号：US20210272984A1

    公开(公告)日：2021-09-02

    申请号：US17024351

    申请日：2020-09-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chien Yao HUANG ,  Wun-Jie LIN ,  Kuo-Ji CHEN

    IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L27/092 ,  G06F30/392

    摘要： An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

    CAPACITOR CELL AND STRUCTURE THEREOF
    3.
    发明申请
    CAPACITOR CELL AND STRUCTURE THEREOF 审中-公开

    公开(公告)号：US20200035681A1

    公开(公告)日：2020-01-30

    申请号：US16591064

    申请日：2019-10-02

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chien-Yao HUANG ,  Wun-Jie LIN ,  Chia-Wei HSU ,  Yu-Ti SU

    IPC分类号： H01L27/092 ,  H01L29/94 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

    摘要： A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES
    4.
    发明公开
    ELECTROSTATIC DISCHARGE (ESD) ARRAY WITH CIRCUIT CONTROLLED SWITCHES 审中-公开

    公开(公告)号：US20240321781A1

    公开(公告)日：2024-09-26

    申请号：US18731021

    申请日：2024-05-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Tao-Yi HUNG ,  Wun-Jie LIN ,  Jam-Wem LEE ,  Kuo-Ji CHEN

    IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H9/04

    CPC分类号： H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

    摘要： An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

    CAPACITOR CELL AND STRUCTURE THEREOF
    7.
    发明申请
    CAPACITOR CELL AND STRUCTURE THEREOF 审中-公开

    公开(公告)号：US20180308846A1

    公开(公告)日：2018-10-25

    申请号：US15495106

    申请日：2017-04-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chien-Yao HUANG ,  Wun-Jie LIN ,  Chia-Wei HSU ,  Yu-Ti SU

    IPC分类号： H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

    摘要： A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.

    ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS
    9.
    发明申请
    ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS 有权

    公开(公告)号：US20220320075A1

    公开(公告)日：2022-10-06

    申请号：US17219495

    申请日：2021-03-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yu-Hung YEH ,  Wun-Jie LIN ,  Jam-Wern LEE

    IPC分类号： H01L27/02 ,  H01L23/522 ,  H01L23/535

    摘要： An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM
    10.
    发明申请
    INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM 有权

    公开(公告)号：US20220037365A1

    公开(公告)日：2022-02-03

    申请号：US16940930

    申请日：2020-07-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chien Yao HUANG ,  Wun-Jie LIN ,  Kuo-Ji CHEN

    IPC分类号： H01L27/118 ,  G06F30/392 ,  H01L21/8238 ,  H01L27/02

    摘要： An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.