公开(公告)号：US20240178216A1

公开(公告)日：2024-05-30

申请号：US18435938

申请日：2024-02-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Li-Wei CHU ,  Ming-Fu TSAI ,  Jam-Wem LEE ,  Yu-Ti SU

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/62 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0652 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/747 ,  H01L29/8611 ,  H01L2924/13034 ,  H01L2924/13035

Abstract: A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

公开(公告)号：US20220231010A1

公开(公告)日：2022-07-21

申请号：US17150782

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao-Yi HUNG ,  Wun-Jie LIN ,  Jam-Wem LEE ,  Kuo-Ji CHEN

IPC: H01L27/02 ,  H02H9/04

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

公开(公告)号：US20210082906A1

公开(公告)日：2021-03-18

申请号：US16575091

申请日：2019-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Li-Wei CHU ,  Ming-Fu TSAI ,  Jam-Wem LEE ,  Yu-Ti SU

IPC: H01L27/02 ,  H01L29/87

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US20180151554A1

公开(公告)日：2018-05-31

申请号：US15393723

申请日：2016-12-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Han-Jen YANG ,  Jam-Wem LEE ,  Li-Wei CHU

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L27/07 ,  H01L23/528

Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

公开(公告)号：US20140217461A1

公开(公告)日：2014-08-07

申请号：US14251670

申请日：2014-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsiang SONG ,  Jam-Wem LEE ,  Tzu-Heng CHANG ,  Yu-Ying HSU

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

Abstract translation: ESD保护电路至少包括第一和第二可控硅整流器（SCR）电路。 第一SCR电路耦合在焊盘和正电源端子之间。 第二SCR电路耦合在焊盘和接地端子之间。 SCR电路中的至少一个被配置为选择性地在焊盘和正电源端子和接地端子之一之间提供短路或相对导电的电路径。

公开(公告)号：US20240321781A1

公开(公告)日：2024-09-26

申请号：US18731021

申请日：2024-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi HUNG ,  Wun-Jie LIN ,  Jam-Wem LEE ,  Kuo-Ji CHEN

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US20240222363A1

公开(公告)日：2024-07-04

申请号：US18605645

申请日：2024-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Li-Wei CHU ,  Ming-Fu TSAI ,  Jam-Wem LEE ,  Yu-Ti SU

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/62 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0652 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/747 ,  H01L29/8611 ,  H01L2924/13034 ,  H01L2924/13035

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US20230326920A1

公开(公告)日：2023-10-12

申请号：US18210472

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung YEH ,  Wun-Jie LIN ,  Jam-Wem LEE

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H02H9/046 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

公开(公告)号：US20220208753A1

公开(公告)日：2022-06-30

申请号：US17699493

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Li-Wei CHU ,  Ming-Fu TSAI ,  Jam-Wem LEE ,  Yu-Ti SU

IPC: H01L27/02 ,  H01L29/87

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

公开(公告)号：US20190067281A1

公开(公告)日：2019-02-28

申请号：US15691725

申请日：2017-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Feng CHANG ,  Po-Lin PENG ,  Jam-Wem LEE

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/87

Abstract: A semiconductor device includes a first active area of a first type, a second active area of a second type, and a plurality of gates. The gates are arranged above and across the first active area and the second active area. At a first side of a first gate of the plurality of gates, a first region of the first active area is configured to receive a first voltage and a first region of the second active area is configured to receive a second voltage. At a second side of the first gate, a second region of the first active area is disconnected from the first voltage and a second region of the second active area is disconnected from the second voltage.