公开(公告)号：US11706928B2

公开(公告)日：2023-07-18

申请号：US17166078

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L51/30 ,  H01L29/78 ,  H10B51/30 ,  H01L29/66

CPC classification number: H10B51/30 ,  H01L29/6684 ,  H01L29/78391

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

公开(公告)号：US20220285519A1

公开(公告)日：2022-09-08

申请号：US17319461

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.