公开(公告)号：US10931103B2

公开(公告)日：2021-02-23

申请号：US16143315

申请日：2018-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hung Chen ,  Kuo-Ji Chen ,  Shao-Yu Chou

IPC: H02H9/04 ,  H03K17/082 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

公开(公告)号：US10535602B2

公开(公告)日：2020-01-14

申请号：US16202708

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Shao-Tung Peng ,  Shao-Yu Chou ,  Liang Chuan Chang ,  Yao-Jen Yang

IPC: G11C17/18 ,  H01L23/525 ,  G11C17/16 ,  H01H85/046 ,  H01H85/05 ,  H01L23/50

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

公开(公告)号：US20190287900A1

公开(公告)日：2019-09-19

申请号：US16202708

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Shao-Tung Peng ,  Shao-Yu Chou ,  Liang Chuan Chang ,  Yao-Jen Yang

IPC: H01L23/525 ,  H01H85/046 ,  H01L23/50 ,  H01H85/05 ,  G11C17/18 ,  G11C17/16

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

公开(公告)号：US10269420B2

公开(公告)日：2019-04-23

申请号：US15619084

申请日：2017-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang Chen ,  Shao-Yu Chou ,  Chun-Hao Chang ,  Min-Shin Wu ,  Yu-Der Chih

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C11/413 ,  G11C7/10

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

公开(公告)号：US09853035B2

公开(公告)日：2017-12-26

申请号：US14589009

申请日：2015-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.