公开(公告)号：US12243618B2

公开(公告)日：2025-03-04

申请号：US18164274

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: G11C7/10 ,  G11C5/06 ,  G11C8/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  H10B20/25

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

公开(公告)号：US10163783B1

公开(公告)日：2018-12-25

申请号：US15922439

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Shao-Tung Peng ,  Shao-Yu Chou ,  Liang Chuan Chang ,  Yao-Jen Yang

IPC: G11C17/18 ,  H01L23/525 ,  G11C17/16 ,  H01H85/046 ,  H01H85/05 ,  H01L23/50

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

公开(公告)号：US12230359B2

公开(公告)日：2025-02-18

申请号：US18164282

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: G11C7/10 ,  G11C5/06 ,  G11C8/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  H10B20/25

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US11569248B2

公开(公告)日：2023-01-31

申请号：US16990995

申请日：2020-08-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang

IPC: H01L27/112 ,  G11C17/16

Abstract: An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

公开(公告)号：US11257827B2

公开(公告)日：2022-02-22

申请号：US16729973

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  H01L27/112 ,  H01L23/528 ,  G06F30/392 ,  G11C17/18 ,  H01L23/522 ,  G11C17/16

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

公开(公告)号：US10535602B2

公开(公告)日：2020-01-14

申请号：US16202708

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Shao-Tung Peng ,  Shao-Yu Chou ,  Liang Chuan Chang ,  Yao-Jen Yang

IPC: G11C17/18 ,  H01L23/525 ,  G11C17/16 ,  H01H85/046 ,  H01H85/05 ,  H01L23/50

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

公开(公告)号：US20190287900A1

公开(公告)日：2019-09-19

申请号：US16202708

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Shao-Tung Peng ,  Shao-Yu Chou ,  Liang Chuan Chang ,  Yao-Jen Yang

IPC: H01L23/525 ,  H01H85/046 ,  H01L23/50 ,  H01H85/05 ,  G11C17/18 ,  G11C17/16

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

公开(公告)号：US12063773B2

公开(公告)日：2024-08-13

申请号：US17589580

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/528 ,  H10B20/20

CPC classification number: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

公开(公告)号：US11600626B2

公开(公告)日：2023-03-07

申请号：US16713967

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Yih Wang ,  Fu-An Wu

IPC: H01L27/112 ,  G11C7/10 ,  H01L23/522 ,  G11C17/16 ,  H01L23/525 ,  G11C5/06 ,  G11C8/08 ,  G11C17/18

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US20210202503A1

公开(公告)日：2021-07-01

申请号：US16729973

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: H01L27/112 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G06F30/392

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.