公开(公告)号：US20240389472A1

公开(公告)日：2024-11-21

申请号：US18786688

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Lin Huang ,  MingYuan Song ,  Chien-Min Lee ,  Shy-Jay Lin ,  Chi-Feng Pai ,  Chen-Yu Hu ,  Chao-Chung Huang ,  Kuan-Hao Chen ,  Chia-Chin Tsai ,  Yu-Fang Chiu ,  Cheng-Wei Peng

IPC: H10N50/85 ,  C22C5/04 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

公开(公告)号：US12022665B2

公开(公告)日：2024-06-25

申请号：US18335816

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H10B61/00

CPC classification number: H10B61/22 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/528

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

公开(公告)号：US20230345738A1

公开(公告)日：2023-10-26

申请号：US18335816

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

IPC: H10B61/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H10B61/22 ,  H01L23/528 ,  H01L21/76898 ,  H01L21/823475

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.