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公开(公告)号：US11682468B2
公开(公告)日：2023-06-20
申请号：US17740302
申请日：2022-05-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hiroki Noguchi
Abstract: A memory system is provided. The memory system includes a compare circuit and a control circuit. The compare circuit determines, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table. The control circuit increments a counter value corresponding to the fail word address when the fail word address is in the error table, and further compares the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.
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公开(公告)号：US11328788B2
公开(公告)日：2022-05-10
申请号：US17011991
申请日：2020-09-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hiroki Noguchi
Abstract: A memory system is disclosed. The memory system includes a first memory array, an error correction code circuit, and a monitor circuit. The error correction code circuit is configured to receive data from the first memory array to correct, at least one error bit in the received data. The error correction code circuit is further configured to generate an error determination signal. The monitor circuit is coupled to the error correction code circuit. The monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.
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公开(公告)号：US11183261B2
公开(公告)日：2021-11-23
申请号：US16836928
申请日：2020-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.
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公开(公告)号：US20210271479A1
公开(公告)日：2021-09-02
申请号：US16923107
申请日：2020-07-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Yih Wang
Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.
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公开(公告)号：US20210271417A1
公开(公告)日：2021-09-02
申请号：US16985240
申请日：2020-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Shih-Lien Linus Lu , Yu-Der Chih , Yih Wang
Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
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Patent Agency Ranking
公开(公告)号：US12225734B2
公开(公告)日：2025-02-11
申请号：US17815000
申请日：2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , Mingyuan Song , Hiroki Noguchi
Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.
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公开(公告)号：US20240381668A1
公开(公告)日：2024-11-14
申请号：US18781094
申请日：2024-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , MingYuan Song , Hiroki Noguchi
Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.
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公开(公告)号：US12125551B2
公开(公告)日：2024-10-22
申请号：US17874973
申请日：2022-07-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ku-Feng Lin , Hiroki Noguchi
CPC classification number: G11C7/062 , G11C11/16 , G11C13/004
Abstract: A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.
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公开(公告)号：US11681468B2
公开(公告)日：2023-06-20
申请号：US16985240
申请日：2020-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hiroki Noguchi , Shih-Lien Linus Lu , Yu-Der Chih , Yih Wang
CPC classification number: G06F3/0659 , G06F1/28 , G06F3/0604 , G06F3/0673 , G06F9/4893
Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
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公开(公告)号：US12022665B2
公开(公告)日：2024-06-25
申请号：US18335816
申请日：2023-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , Chien-Min Lee , Hiroki Noguchi , MingYuan Song , Yen-Lin Huang , William Joseph Gallagher
IPC: H01L21/00 , H01L21/768 , H01L21/8234 , H01L23/528 , H10B61/00
CPC classification number: H10B61/22 , H01L21/76898 , H01L21/823475 , H01L23/528
Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.
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