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    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11063217B2

    公开(公告)日：2021-07-13

    申请号：US16983928

    申请日：2020-08-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

    IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

    Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.

    Method for fabricating memory device
    6.
    发明授权
    Method for fabricating memory device 有权

    公开(公告)号：US10971682B2

    公开(公告)日：2021-04-06

    申请号：US16866101

    申请日：2020-05-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

    IPC: H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

    Abstract: A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

    Semiconductor Device and Method for Forming the Same
    8.
    发明申请
    Semiconductor Device and Method for Forming the Same 有权

    公开(公告)号：US20210408115A1

    公开(公告)日：2021-12-30

    申请号：US17216162

    申请日：2021-03-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  Hiroki Noguchi ,  MingYuan Song ,  Yen-Lin Huang ,  William Joseph Gallagher

    IPC: H01L27/22 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528

    Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

    STRAINED FERROMAGNETIC HALL METAL SOT LAYER
    9.
    发明申请
    STRAINED FERROMAGNETIC HALL METAL SOT LAYER 有权

    公开(公告)号：US20210359199A1

    公开(公告)日：2021-11-18

    申请号：US17144958

    申请日：2021-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shy-Jay Lin ,  Chien-Min Lee ,  MingYuan Song

    IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

    Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.

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