公开(公告)号：US20190157281A1

公开(公告)日：2019-05-23

申请号：US16204840

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42344 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20180061847A1

公开(公告)日：2018-03-01

申请号：US15272067

申请日：2016-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ling SHIH ,  Chieh-Fei CHIU ,  Po-Wei LIU ,  Tsun-Kai TSAO ,  Wen-Tuo HUANG ,  Yu-Ling HSU ,  Yong-Shiuan TSAIR

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.

公开(公告)号：US20210225857A1

公开(公告)日：2021-07-22

申请号：US17226348

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20210118876A1

公开(公告)日：2021-04-22

申请号：US16657396

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/423 ,  H01L29/40

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US20200161317A1

公开(公告)日：2020-05-21

申请号：US16748584

申请日：2020-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20180315764A1

公开(公告)日：2018-11-01

申请号：US15498743

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Hung-Ling SHIH ,  Chieh-Fei CHIU ,  Po-Wei LIU ,  Wen-Tuo HUANG ,  Yu-Ling HSU ,  Yong-Shiuan TSAIR

IPC: H01L27/11521 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30625 ,  H01L21/3065 ,  H01L29/42344 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°