公开(公告)号：US20220013494A1

公开(公告)日：2022-01-13

申请号：US16924192

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

公开(公告)号：US11127708B2

公开(公告)日：2021-09-21

申请号：US16676439

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

公开(公告)号：US10978782B2

公开(公告)日：2021-04-13

申请号：US16858743

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q1/38 ,  H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01Q9/04 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

公开(公告)号：US20200075526A1

公开(公告)日：2020-03-05

申请号：US16676439

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

公开(公告)号：US20190096841A1

公开(公告)日：2019-03-28

申请号：US15717974

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

公开(公告)号：US10937719B2

公开(公告)日：2021-03-02

申请号：US15638386

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Nien-Fang Wu ,  Shou-Zen Chang ,  Yi-Che Chiang

IPC: H01L23/495 ,  H01L23/66 ,  H01L25/16 ,  H01P1/30 ,  H01P3/02 ,  H01L23/31 ,  H01L23/433 ,  H01Q21/06 ,  H01L21/56 ,  H01Q15/00 ,  H01Q1/22 ,  H01L21/683 ,  H01P1/20 ,  H01L23/538 ,  H01L23/498

Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.

公开(公告)号：US20200335439A1

公开(公告)日：2020-10-22

申请号：US16389992

申请日：2019-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Chang-Wen Huang ,  Yu-Sheng Hsieh ,  Ching-Yu Huang

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.

公开(公告)号：US10157807B2

公开(公告)日：2018-12-18

申请号：US15235106

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01Q9/04 ,  H01L21/56

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

公开(公告)号：US20180269139A1

公开(公告)日：2018-09-20

申请号：US15638386

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Nien-Fang Wu ,  Shou-Zen Chang ,  Yi-Che Chiang

IPC: H01L23/495 ,  H01L23/66 ,  H01L25/16 ,  H01P1/30 ,  H01P3/02 ,  H01L23/31 ,  H01L23/433

CPC classification number: H01L23/49548 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49575 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/162 ,  H01L25/165 ,  H01L2224/18 ,  H01P1/2005 ,  H01P1/30 ,  H01P3/026 ,  H01Q1/2283 ,  H01Q15/0086 ,  H01Q21/062

Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.

公开(公告)号：US20200258799A1

公开(公告)日：2020-08-13

申请号：US16858743

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q1/22 ,  H01Q21/06 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01Q9/04

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.