公开(公告)号：US11004809B2

公开(公告)日：2021-05-11

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping Chiang ,  Yi-Che Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00 ,  H01L21/56 ,  H01L23/538 ,  H01Q1/22 ,  H01Q21/22

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20200020628A1

公开(公告)日：2020-01-16

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US11335666B2

公开(公告)日：2022-05-17

申请号：US16924192

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

公开(公告)号：US11075159B2

公开(公告)日：2021-07-27

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L21/768

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US10312203B2

公开(公告)日：2019-06-04

申请号：US15625678

申请日：2017-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yung-Ping Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Yi-Che Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20170345731A1

公开(公告)日：2017-11-30

申请号：US15235106

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01L23/528 ,  H01Q9/04 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66

CPC classification number: H01L23/3107 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/528 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01Q1/2283 ,  H01Q9/04 ,  H01Q21/065

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

公开(公告)号：US09343415B2

公开(公告)日：2016-05-17

申请号：US14690570

申请日：2015-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Wen Shih ,  Yung-Ping Chiang ,  Chen-Chih Hsieh ,  Hao-Yi Tsai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/9212 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01029

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

公开(公告)号：US09035468B2

公开(公告)日：2015-05-19

申请号：US13954046

申请日：2013-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chao-Wen Shih ,  Yung-Ping Chiang ,  Chen-Chih Hsieh ,  Hao-Yi Tsai

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/9212 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01029

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract translation: 在形成封装结构的方法中，在半导体衬底上形成金属焊盘，在半导体衬底上形成第一高分子绝缘层。 形成穿过第一聚合物绝缘层的开口以暴露金属垫的一部分。 在第一聚合物绝缘层的开口内和第一聚合物绝缘层上沉积含铜材料，从而在第一聚合物绝缘层上形成具有第一厚度和第一宽度的含铜层。 在含铜层上形成具有第二宽度的导电凸块，其中第二宽度小于第一宽度。 使用导电凸块作为掩模蚀刻含铜层的暴露部分，直到暴露部分被还原成第二厚度，从而形成整体含铜结构。

公开(公告)号：US20150035139A1

公开(公告)日：2015-02-05

申请号：US13954046

申请日：2013-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chao-Wen Shih ,  Yung-Ping Chiang ,  Chen-Chih Hsieh ,  Hao-Yi Tsai

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/9212 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01029

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract translation: 在形成封装结构的方法中，在半导体衬底上形成金属焊盘，在半导体衬底上形成第一高分子绝缘层。 形成穿过第一聚合物绝缘层的开口以暴露金属垫的一部分。 在第一聚合物绝缘层的开口内和第一聚合物绝缘层上沉积含铜材料，从而在第一聚合物绝缘层上形成具有第一厚度和第一宽度的含铜层。 在含铜层上形成具有第二宽度的导电凸块，其中第二宽度小于第一宽度。 使用导电凸块作为掩模蚀刻含铜层的暴露部分，直到暴露部分被还原成第二厚度，从而形成整体含铜结构。

公开(公告)号：US20250167161A1

公开(公告)日：2025-05-22

申请号：US18585854

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jin Hu ,  Hua-Wei Tseng ,  Wei-Cheng Wu ,  Yung-Ping Chiang ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.