公开(公告)号：US11004809B2

公开(公告)日：2021-05-11

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping Chiang ,  Yi-Che Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00 ,  H01L21/56 ,  H01L23/538 ,  H01Q1/22 ,  H01Q21/22

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20240234340A1

公开(公告)日：2024-07-11

申请号：US18151545

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Yuan Sheng Chiu ,  Hong-Yu Guo ,  Hsin-Yu Pan ,  Tsung-Shu Lin

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2924/0544 ,  H01L2924/05494

Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.

公开(公告)号：US11018113B2

公开(公告)日：2021-05-25

申请号：US16655237

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Hao Tsai ,  Hsin-Yu Pan ,  Yi-Che Chiang ,  Chien-Chang Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/367

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure. The thermally conductive material is disposed on the second redistribution structure, among the second semiconductor dies and overlying the through insulator vias. The thermally conductive material has a thermal conductivity larger than that of the encapsulant.

公开(公告)号：US10748831B2

公开(公告)日：2020-08-18

申请号：US15992196

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/36 ,  H01L23/52 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.

公开(公告)号：US20190371694A1

公开(公告)日：2019-12-05

申请号：US15992196

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.

公开(公告)号：US20230223357A1

公开(公告)日：2023-07-13

申请号：US17752272

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Chien-Hsun Chen ,  Tuan-Yu Hung ,  Hsin-Yu Pan ,  Wei-Kang Hsieh ,  Tsung-Hsien Chiang ,  Chao-Hsien Huang ,  Tzu-Sung Huang ,  Ming Hung Tseng ,  Wei-Chih Chen ,  Ban-Li Wu ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/214 ,  H01L2221/68359 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

公开(公告)号：US20210118847A1

公开(公告)日：2021-04-22

申请号：US16655237

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Hao Tsai ,  Hsin-Yu Pan ,  Yi-Che Chiang ,  Chien-Chang Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure. The thermally conductive material is disposed on the second redistribution structure, among the second semiconductor dies and overlying the through insulator vias. The thermally conductive material has a thermal conductivity larger than that of the encapsulant.

公开(公告)号：US20200373219A1

公开(公告)日：2020-11-26

申请号：US16993285

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

公开(公告)号：US11532576B2

公开(公告)日：2022-12-20

申请号：US16787020

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Yi-Che Chiang

IPC: H01L21/66 ,  H01L27/146 ,  H01L23/00 ,  G01R31/28

Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.

公开(公告)号：US11373922B2

公开(公告)日：2022-06-28

申请号：US16993285

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/52 ,  H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.