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    Dummy fin with reduced height and method forming same
    11.
    发明授权
    Dummy fin with reduced height and method forming same 有权

    公开(公告)号：US11410886B2

    公开(公告)日：2022-08-09

    申请号：US16942076

    申请日：2020-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Te-Yung Liu ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/092

    Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

    Multi-Channel Devices and Methods of Manufacture
    13.
    发明申请
    Multi-Channel Devices and Methods of Manufacture 有权

    公开(公告)号：US20220181214A1

    公开(公告)日：2022-06-09

    申请号：US17682604

    申请日：2022-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

    IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

    Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

    Semiconductor devices and methods of formation
    14.
    发明授权
    Semiconductor devices and methods of formation 有权

    公开(公告)号：US11289585B2

    公开(公告)日：2022-03-29

    申请号：US16889427

    申请日：2020-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

    Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

    DEVICE WITH A DUMMY FIN CONTACTING A GATE ISOLATION REGION
    19.
    发明申请
    DEVICE WITH A DUMMY FIN CONTACTING A GATE ISOLATION REGION 有权

    公开(公告)号：US20240379818A1

    公开(公告)日：2024-11-14

    申请号：US18779849

    申请日：2024-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yao Lin ,  Chih-Han Lin

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

    Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

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