公开(公告)号：US20220344484A1

公开(公告)日：2022-10-27

申请号：US17548133

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Hsuan Chen ,  Ping-Wei Wang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/308 ,  H01L29/40

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

公开(公告)号：US12218227B2

公开(公告)日：2025-02-04

申请号：US18447932

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chia-Hung Chou ,  Chih-Hsuan Chen ,  Ping-En Cheng ,  Hsin-Wen Su ,  Chien-Chih Lin ,  Szu-Chi Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

公开(公告)号：US11996484B2

公开(公告)日：2024-05-28

申请号：US17319695

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Hsuan Chen ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Hsin-Wen Su ,  Chia-Wei Chen

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78621 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/167 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/456

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

公开(公告)号：US11949016B2

公开(公告)日：2024-04-02

申请号：US17319794

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Chih-Hsuan Chen ,  Bwo-Ning Chen ,  Cha-Hon Chou ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L29/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

公开(公告)号：US20220367728A1

公开(公告)日：2022-11-17

申请号：US17319695

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Hsuan Chen ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Hsin-Wen Su ,  Chia-Wei Chen

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/167

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.