Integrated communication link testing

    公开(公告)号:US12222388B2

    公开(公告)日:2025-02-11

    申请号:US18488936

    申请日:2023-10-17

    Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

    INTEGRATED COMMUNICATION LINK TESTING

    公开(公告)号:US20210270893A1

    公开(公告)日:2021-09-02

    申请号:US17324007

    申请日:2021-05-18

    Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

    Passive variable continuous time linear equalizer with attenuation and frequency control

    公开(公告)号:US10904042B2

    公开(公告)日:2021-01-26

    申请号:US16116677

    申请日:2018-08-29

    Abstract: A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.

    DUAL OUTPUT SIGNAL PATHS FOR SIGNAL SOURCE CHANNELS TO OPTIMIZE FOR BANDWIDTH AND AMPLITUDE RANGE

    公开(公告)号:US20200212926A1

    公开(公告)日:2020-07-02

    申请号:US16588613

    申请日:2019-09-30

    Abstract: A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.

    INTEGRATED COMMUNICATION LINK TESTING
    17.
    发明申请

    公开(公告)号:US20190383873A1

    公开(公告)日:2019-12-19

    申请号:US16440944

    申请日:2019-06-13

    Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

    Joint Optimization of FIR Filters in a Non-Linear Compensator

    公开(公告)号:US20190312571A1

    公开(公告)日:2019-10-10

    申请号:US15948121

    申请日:2018-04-09

    Abstract: A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.

    NOISE REDUCTION IN DIGITIZING SYSTEMS
    19.
    发明申请

    公开(公告)号:US20170328932A1

    公开(公告)日:2017-11-16

    申请号:US15395416

    申请日:2016-12-30

    CPC classification number: G01R13/0218 G01R13/0272 H03M1/0626 H03M1/12

    Abstract: Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.

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