公开(公告)号：US07711241B2

公开(公告)日：2010-05-04

申请号：US10714917

申请日：2003-11-18

申请人： Yasuhiro Mori ,  Ichiro Okabayashi ,  Masaki Yamauchi ,  Akihiro Kawabata

发明人： Yasuhiro Mori ,  Ichiro Okabayashi ,  Masaki Yamauchi ,  Akihiro Kawabata

IPC分类号： G11B27/00

CPC分类号： H04N5/445 ,  G11B27/034 ,  G11B27/105 ,  G11B27/34 ,  H04M1/72555 ,  H04N5/4401 ,  H04N5/765 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N21/234336 ,  H04N21/482 ,  H04N21/8153 ,  H04N21/854

摘要： A short film generation/reproduction apparatus for generating video of a short film using at least one still picture and reproducing such video is comprised of: a picture feature extraction unit 1107 for extracting picture features from an input picture; a picture-to-style feature conversion unit 1115 for converting the picture features into style features; a picture-to-musical feature conversion unit 1118 for converting the picture features into musical features; a style determination unit 1116 for determining a style based on the style features; a music determination unit 1119 for determining a piece of music based on the musical features; and a scenario generation unit 1117 for generating a scenario by using the still picture, music and style.

摘要翻译： 一种用于使用至少一个静止图像产生短片的视频并再现这样的视频的短片生成/再现装置包括：用于从输入图像中提取图像特征的图像特征提取单元1107; 用于将图片特征转换成风格特征的图片到样式的特征转换单元1115; 用于将图像特征转换成音乐特征的图像到音乐特征转换单元1118; 风格确定单元1116，用于基于风格特征确定风格; 用于基于音乐特征确定一段音乐的音乐确定单元1119; 以及用于通过使用静止图像，音乐和风格来生成场景的场景生成单元1117。

公开(公告)号：US5652614A

公开(公告)日：1997-07-29

申请号：US633618

申请日：1996-04-17

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F3/06 ,  G06F3/08 ,  H04N7/173

CPC分类号： G11B20/10527 ,  H04N7/17336 ,  G11B2020/10638

摘要： Image and sound data stored in an optical disc unit having an medium auto-changer mechanism are read out and temporarily stored in a hard disk unit, after then supplied to a user's terminal unit via a memory which serves as an output buffer. The image and sound data are stored in the memory, by compressing and a time length required to read out the data is shorter than a reproduction time in the user's terminal unit, and therefore plural data are read out by a difference between a readout time and the reproduction time. Since write operation to the hard disk unit and readout operation from the hard disk unit to write to the main memory 3 are simultaneously carried out, plural hard disk units are disposed and accessed in parallel. Moreover, a unit of data in write operation is larger than a unit of data in readout operation in the hard disk unit.

摘要翻译： 存储在具有中等自动更换机构的光盘单元中的图像和声音数据被读出并临时存储在硬盘单元中，然后经由用作输出缓冲器的存储器提供给用户的终端单元。 图像和声音数据通过压缩存储在存储器中，读出数据所需的时间长度短于用户终端单元中的再现时间，因此通过读出时间和 再现时间。 由于同时执行对硬盘单元的写入操作和从硬盘单元读取操作以写入主存储器3，所以并行地布置和访问多个硬盘单元。 此外，写入操作中的数据单位大于硬盘单元中的读出操作中的数据单位。

公开(公告)号：US5408613A

公开(公告)日：1995-04-18

申请号：US995873

申请日：1992-12-23

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F13/14

CPC分类号： G06F15/17 ,  G06F15/17381

摘要： A parallel processing system enabling a mixed transfer of packets of different lengths is achieved.The data transfer apparatus in this parallel processing system comprises four address controllers. During the first data transfer the third address controller is used for sending and the first address controller is used for receiving data. During the second transfer, the fourth address controller is used for sending, and the second address controller is used for receiving.When the first and second transfer operations are mixed, the first and second address controllers are selectively used during receiving, and the third and fourth address controllers are selectively used during sending. Each of the address controllers changes the address only after packet transfer is completed. The header of the packet contains a packet length field, which is interpreted to enable simultaneous, dynamic handling of plural packets of different lengths.As a result, packets can be transferred without deadlocks occurring even when packets of different lengths are mixed.

摘要翻译： 实现了能够进行不同长度的分组的混合传送的并行处理系统。 该并行处理系统中的数据传送装置包括四个地址控制器。 在第一次数据传输期间，第三个地址控制器用于发送，第一个地址控制器用于接收数据。 在第二次传送期间，第四地址控制器用于发送，第二地址控制器用于接收。 当第一和第二传送操作混合时，在接收期间选择性地使用第一和第二地址控制器，并且在发送期间选择性地使用第三和第四地址控制器。 每个地址控制器只有在数据包传输完成后才能更改地址。 分组的报头包含分组长度字段，其被解释为能够同时，动态地处理不同长度的多个分组。 结果，即使在混合了不同长度的数据包的情况下，也可以传送分组而不发生死锁。

公开(公告)号：US5838362A

公开(公告)日：1998-11-17

申请号：US539106

申请日：1995-10-04

申请人： Shinji Furuya ,  Tadashi Okamoto ,  Ichiro Okabayashi ,  Shinji Sasaki

发明人： Shinji Furuya ,  Tadashi Okamoto ,  Ichiro Okabayashi ,  Shinji Sasaki

IPC分类号： H04N5/93 ,  H04N7/173 ,  H04N21/239 ,  H04N21/262 ,  H04N21/2668

CPC分类号： H04N7/17336

摘要： A data readout time adjuster to be used for a video-on-demand system includes the following units. A readout time adjusting data storage unit stores image data for adjusting readout time to be provided to subscribers who have not been assigned the readout right and are waiting for a start of a readout operation. The image data for adjusting readout time cause no inconvenience even if a transmission of the image data is interrupted any time. A readout start position check unit checks an expected time of an occurrence of the readout right and a readout start position at the expected time in response to an additional data transmission request. A readout control unit makes at least one of the readout unit and a private readout unit exclusively provided or the readout time adjusting data storage unit read the image data for adjusting readout time stored in the readout time adjusting data storage unit until the time of the occurrence of the readout right, for the subscribers who have checked the expected time and the readout start position. A readout time adjusting data transmission control unit controls the transmission unit to transmit the image data for adjusting readout time read by the readout control unit to the subscribers who are waiting for the readout right until the time of the occurrence of the readout right.

摘要翻译： 用于视频点播系统的数据读出时间调节器包括以下单元。 读出时间调整数据存储单元存储用于调整读取时间的图像数据，以提供给尚未被分配读出权并且正在等待读出操作开始的用户。 即使图像数据的发送在任何时候都被中断，用于调整读出时间的图像数据也不会造成不便。 读出开始位置检查单元响应于附加数据传输请求，在期望时间检查读出权的发生的预期时间和读出开始位置。 读出控制单元使读出单元和专用读出单元中的至少一个专门设置，或者读出时间调整数据存储单元读取用于调整读出时间调整数据存储单元中存储的读出时间的图像数据，直到发生时 对于已经检查了预期时间的用户和读出开始位置的读出权。 读出时间调整数据发送控制单元控制发送单元将用于将读出控制单元读出的读出时间的图像数据发送给正在等待读出权的用户，直到出现读出权。

公开(公告)号：US5519880A

公开(公告)日：1996-05-21

申请号：US312543

申请日：1994-09-26

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F13/40 ,  G06F15/17 ,  G06F13/00

CPC分类号： G06F15/17 ,  G06F13/4022

摘要： A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor includes a processor, a memory and a data transfer apparatus, all connected to a common bus. The data transfer apparatus includes of three buffers, while a data relay includes two buffers. In data transfer from a processor element to another processor element, a data is relayed in a third processor element only with use of a buffer, or a write/read operation is not performed in the third processor element. Then, the overhead is decreased and the transfer capability is improved. Further, the data transfer apparatus does not access the common bus, so that the width of the bus can be increased, and the processing performance of the processor can be improved.

摘要翻译： 并行处理系统由多个处理器元件和用于将处理器元件彼此连接的网络组成。 处理器包括处理器，存储器和数据传输装置，全部连接到公共总线。 数据传送装置包括三个缓冲器，而数据中继器包括两个缓冲器。 在从处理器元件到另一个处理器元件的数据传输中，数据仅在使用缓冲器的情况下在第三处理器元件中被中继，或者在第三处理器元件中不执行写入/读取操作。 然后，开销降低，转移能力提高。 此外，数据传送装置不访问公共总线，从而可以增加总线的宽度，并且可以提高处理器的处理性能。

公开(公告)号：US5485582A

公开(公告)日：1996-01-16

申请号：US011698

申请日：1993-02-01

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  H01J1/00

CPC分类号： G06F13/28

摘要： At data transfer, a processor sends an address to an address bus and sends a data to a data bus. In a transfer control unit, a comparator compares an outside address signal inputted via the address bus with an inside address signal generated in an address generating part. When the signals coincide with each other, the comparator outputs a coincidence signal. Receiving the coincidence signal, a control part sends a write signal to a buffer and a data on the data bus is stored in the buffer. The address generating part proceeds to a next address according to the write signal. The data in the buffer is sent outside from a port thereafter. Thus, a program for high-speed data transfer is easily programmed with an ordinary code of a processor for general purpose.

摘要翻译： 在数据传输时，处理器将地址发送到地址总线，并将数据发送到数据总线。 在传送控制单元中，比较器将经由地址总线输入的外部地址信号与在地址生成部中生成的内部地址信号进行比较。 当信号彼此一致时，比较器输出一致信号。 接收到一致信号时，控制部分向缓冲器发送写信号，数据总线上的数据被存储在缓冲器中。 地址生成部根据写入信号进行下一个地址。 缓冲区中的数据此后从端口发送到外部。 因此，用于高速数据传输的程序可以用通用处理器的普通代码进行编程。

公开(公告)号：US4879687A

公开(公告)日：1989-11-07

申请号：US59763

申请日：1987-06-08

申请人： Tadashi Okamoto ,  Hiroshi Kadota ,  Jiro Miyake ,  Ichiro Okabayashi ,  Yoshinori Maeda

发明人： Tadashi Okamoto ,  Hiroshi Kadota ,  Jiro Miyake ,  Ichiro Okabayashi ,  Yoshinori Maeda

IPC分类号： G06F12/16 ,  G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/20 ,  G11C11/41

CPC分类号： G11C11/41 ,  G06F12/0891 ,  G11C7/1006 ,  G11C7/20

摘要： A memory device includes plural word data storing rows. Each word data storing row is composed of a plurality of data bit cells for storing the word data, and a valid bit cell for indicating the validity of data. The valid bit cell has a reset circuit composed of FETs, and the reset circuits are connected to one reset line. By applying a reset signal to one reset line, plural valid bit cells are reset as a batch.

摘要翻译： 存储装置包括多个字数据存储行。 每个字数据存储行由用于存储字数据的多个数据位单元和用于指示数据有效性的有效位单元组成。 有效位单元具有由FET组成的复位电路，并且复位电路连接到一个复位线。 通过将复位信号施加到一个复位线，多个有效位单元被重新分批。

公开(公告)号：US5253346A

公开(公告)日：1993-10-12

申请号：US556076

申请日：1990-07-23

申请人： Ichiro Okabayashi ,  Hiroshi Kadota ,  Katsuyuki Kaneko

发明人： Ichiro Okabayashi ,  Hiroshi Kadota ,  Katsuyuki Kaneko

IPC分类号： G06F13/38 ,  G06F15/17 ,  G06F15/173

CPC分类号： G06F15/17375 ,  G06F15/17

摘要： A method of data transfer applicable to processing elements which are interconnected by a network to form a multiprocessor system, whereby when a datum is to be transferred from a processing element to the network, the datum is sent to a transfer controller of the processing element at the same time that it is being read out from memory to be used by the processor of the processing element, or as it is being generated from the processor and written into memory. Thus, the system performance can be substantially improved, since the time required to execute each data transfer can be "hidden" within the processor execution time.

公开(公告)号：US5239214A

公开(公告)日：1993-08-24

申请号：US750119

申请日：1991-08-26

申请人： Reiji Segawa ,  Ichiro Okabayashi

发明人： Reiji Segawa ,  Ichiro Okabayashi

IPC分类号： H03K19/094

CPC分类号： H03K19/09429

摘要： An output circuit for a data transfer device includes first and second control inputs, a data input and a data output. The first control input controls whether the data output is generated in accordance with an ordinary type or an open drain type circuit operation, while the second control input controls whether the data output generated in accordance with the ordinary type circuit operation is set to an active state or an inactive state.

摘要翻译： 用于数据传输装置的输出电路包括第一和第二控制输入，数据输入和数据输出。 第一控制输入根据普通类型或开漏型电路操作来控制数据输出是否产生，而第二控制输入控制根据普通型电路操作生成的数据输出是否被设置为活动状态 或非活动状态。

公开(公告)号：US5210713A

公开(公告)日：1993-05-11

申请号：US752788

申请日：1991-08-30

申请人： Ichiro Okabayashi

发明人： Ichiro Okabayashi

IPC分类号： G06F5/00 ,  G06F5/06 ,  G06F15/173 ,  H03M7/46

CPC分类号： H03M7/46

摘要： A first-in first-out memory device for storing a series of numeral signals includes a comparator for comparing each input numeral signal with a preselected numeral signal, and for producing a matching signal when the input numeral signal is the same as the preselected numeral signal, and an unmatching signal when the input numeral signal is not the same as the preselected numeral signal. An up-counter counts the number of repetition of the matching signal. When the input numeral signal is other than the preselected numeral signal, a tag signal representing the numeral signal is produced and, at the same time, a data signal representing the value of the numeral signal is produced. When the input numeral signal is the preselected numeral signal, such as zero, a tag signal representing repetition number signal is produced and, at the same time, the data signal representing the number of repetition of zeros is produced. Such a pair of tag signal and data signal is stored in a memory.

摘要翻译： 用于存储一系列数字信号的先进先出存储器件包括比较器，用于将每个输入数字信号与预选数字信号进行比较，并且当输入数字信号与预选数字信号相同时产生匹配信号 以及当输入数字信号与预选数字信号不相​​同时的不匹配信号。 上计数器对匹配信号的重复次数进行计数。 当输入数字信号不同于预选数字信号时，产生表示数字信号的标签信号，同时产生表示数字信号值的数据信号。 当输入数字信号是诸如零的预选数字信号时，产生表示重复数信号的标签信号，并且同时产生表示零的重复次数的数据信号。 这样的一对标签信号和数据信号被存储在存储器中。