公开(公告)号：US10068977B2

公开(公告)日：2018-09-04

申请号：US15601591

申请日：2017-05-22

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Haian Lin ,  Yunlong Liu ,  Lark Liu ,  Wei Song ,  ZiQiang Zhao

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: G01V1/3808 ,  G01V1/166 ,  G01V1/18 ,  G01V1/247 ,  G01V1/38 ,  G01V1/3852 ,  G01V2210/1427 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835 ,  Y10T24/39

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

公开(公告)号：US20180130789A1

公开(公告)日：2018-05-10

申请号：US15729894

申请日：2017-10-11

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66136 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US20180090490A1

公开(公告)日：2018-03-29

申请号：US15274402

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/088 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/8236 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/7831 ,  H01L29/7835

Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.