公开(公告)号：US10529706B2

公开(公告)日：2020-01-07

申请号：US16392476

申请日：2019-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/36 ,  H01L29/78 ,  H01L29/861

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US10746890B2

公开(公告)日：2020-08-18

申请号：US16101867

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Frank Baiocchi ,  Haian Lin ,  Yunlong Liu ,  Lark Liu ,  Wei Song ,  ZiQiang Zhao

IPC: H01L29/417 ,  G01V1/38 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  G01V1/16 ,  G01V1/18 ,  G01V1/24 ,  H01L29/423

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

公开(公告)号：US20190259745A1

公开(公告)日：2019-08-22

申请号：US16392476

申请日：2019-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861 ,  H01L29/40 ,  H01L29/36 ,  H01L29/78

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US10804263B2

公开(公告)日：2020-10-13

申请号：US15274402

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/088 ,  H01L29/40 ,  H01L29/10 ,  H01L21/8236 ,  H01L29/78 ,  H01L29/417 ,  H01L21/265 ,  H01L29/06

Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.

公开(公告)号：US10707344B2

公开(公告)日：2020-07-07

申请号：US15817488

申请日：2017-11-20

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Yunlong Liu ,  Lark Liu ,  Tianping Lv ,  Peter Lin ,  Ho Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L21/74 ,  H01L29/06 ,  H01L29/10

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

公开(公告)号：US10319712B2

公开(公告)日：2019-06-11

申请号：US15729894

申请日：2017-10-11

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/36 ,  H01L29/861 ,  H01L29/40 ,  H01L29/78

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US09853144B2

公开(公告)日：2017-12-26

申请号：US15171136

申请日：2016-06-02

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Yunlong Liu ,  Lark Liu ,  Tianping Lv ,  Peter Lin ,  Ho Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/768 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/7835

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

公开(公告)号：US09646965B2

公开(公告)日：2017-05-09

申请号：US14608391

申请日：2015-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun Wang ,  Frank Baiocchi ,  Haian Lin

IPC: H01L27/088 ,  H01L29/78 ,  H02M3/155 ,  H02M3/158

CPC classification number: H01L27/088 ,  H01L21/26533 ,  H01L21/761 ,  H01L21/823493 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835 ,  H02M3/1588 ,  Y02B70/1466

Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.

公开(公告)号：US10529705B2

公开(公告)日：2020-01-07

申请号：US16372165

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/36 ,  H01L29/861 ,  H01L29/40 ,  H01L29/78

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US20190229110A1

公开(公告)日：2019-07-25

申请号：US16372165

申请日：2019-04-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861 ,  H01L29/40 ,  H01L29/36 ,  H01L29/78

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.