公开(公告)号：US09967123B1

公开(公告)日：2018-05-08

申请号：US15426464

申请日：2017-02-07

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

IPC: H04L27/00 ,  H04L27/26

CPC classification number: H04L27/2615 ,  H04L27/2634

Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

公开(公告)号：US09923737B2

公开(公告)日：2018-03-20

申请号：US15246248

申请日：2016-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Sreenath Narayanan Potty

IPC: H04L27/14 ,  H03K9/00 ,  H04L25/03 ,  H04L12/741 ,  H04L12/26

CPC classification number: H04L25/03006 ,  H04L43/022 ,  H04L45/745

Abstract: A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.

公开(公告)号：US09025705B2

公开(公告)日：2015-05-05

申请号：US14046479

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Jaiganesh Balakrishnan

IPC: H04L27/08 ,  H04L25/06

CPC classification number: H04L25/061

Abstract: A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including samples at a plurality of sample instances, the samples including a positive sample and a negative sample and represented by first plurality of bits. The biasing circuit generates a biased digital signal by adding a bias value to the digital signal so as to change the positive sample and the negative sample to first sample and second sample respectively and represented by second plurality of bits. The digital baseband circuit is configured to receive and process the biased digital signal such that reduced current consumption is realized based on a number of bit toggles in the second plurality of bits being less than a number of bit toggles in the first plurality of bits.

Abstract translation: 数字电路包括至少一个输入节点，偏置电路和数字基带电路。 输入节点接收包括多个采样实例的采样的数字信号，采样包括正采样和负采样并由第一多个位表示。 偏置电路通过向数字信号添加偏置值来产生偏置数字信号，以分别将正采样和负采样改变为第一采样和第二采样，并由第二多位表示。 数字基带电路被配置为接收和处理偏置的数字信号，使得基于第二多个位中的多个比特切换小于第一多个比特中的比特切换的数量来实现减少的电流消耗。

公开(公告)号：US20150088419A1

公开(公告)日：2015-03-26

申请号：US14034486

申请日：2013-09-23

Applicant: Texas Instruments Incorporated

Inventor： Sachin Bhardwaj ,  Sriram Murali ,  Jaiganesh Balakrishnan ,  Jayawardan Janardhanan ,  Yogesh Shekar ,  Goutam Dutta

IPC: G01C21/16 ,  G01C21/20

CPC classification number: G01C21/165 ,  G01C21/16 ,  G01C21/20

Abstract: According to an aspect of the present disclosure, the relative attitude between an inertial measurement unit (IMU), present on a mobile device, and the frame of reference of the vehicle carrying mobile device is estimated. The estimated relative attitude is used to translate the IMU measurement to the vehicle frame of reference to determine the velocity and position of the vehicle. As a result, the vehicle position and velocity are determined accurately in the event of undocking and re-docking of the mobile device from a docking system in the vehicle. The relative attitude is estimated in terms of pitch, roll, and yaw angles.

Abstract translation: 根据本公开的一个方面，估计出现在移动设备上的惯性测量单元（IMU）与携带移动设备的车辆的参考系之间的相对姿态。 估计的相对姿态用于将IMU测量值转换为车辆参考系，以确定车辆的速度和位置。 结果，在移动设备从车辆中的对接系统脱离和重新对接的情况下，准确地确定车辆位置和速度。 根据俯仰角，俯仰角和偏航角估计相对姿态。

公开(公告)号：US20240356496A1

公开(公告)日：2024-10-24

申请号：US18615831

申请日：2024-03-25

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Jawaharlal Tangudu ,  Manchi Sankalkar Ajay ,  Mathews John ,  Jaiganesh Balakrishnan ,  Neeraj Kumar Sharma

IPC: H03F1/32

CPC classification number: H03F1/3247

Abstract: An example apparatus includes: memory having a terminal, the memory to store machine-readable instructions and adjacent channel leakage data; and programmable circuitry having a terminal coupled to the terminal of the memory, the programmable circuitry to execute the machine-readable instructions to: determine a range of out-of-band frequencies responsive to adjacent channel leakage ratio data; generate weight values responsive to electromagnetic emissions within the range of out-of-band frequencies of a first signal; modify a pre-distortion function responsive to the weight values; and apply the modified pre-distortion function to generate a second signal, the second signal to exhibit fewer emissions in the range of out-of-band frequencies than the first signal during transmission.

公开(公告)号：US20220209807A1

公开(公告)日：2022-06-30

申请号：US17530158

申请日：2021-11-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan

IPC: H04B1/12 ,  H04B1/16 ,  H04H40/72 ,  H04B17/318 ,  H04B17/20 ,  H04B17/336 ,  H04B1/10

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

公开(公告)号：US11239833B2

公开(公告)日：2022-02-01

申请号：US17071302

申请日：2020-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Jaiganesh Balakrishnan ,  Ram Narayan Krishna Nama Mony ,  Pooja Sundar

IPC: H03K5/1252 ,  G11C19/28 ,  G06F1/10 ,  G06F1/08 ,  H03K19/21 ,  H03K5/00

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.

公开(公告)号：US20220029644A1

公开(公告)日：2022-01-27

申请号：US17492710

申请日：2021-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Yeswanth Guntupalli

IPC: H04B1/00

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

公开(公告)号：US10555256B2

公开(公告)日：2020-02-04

申请号：US15259703

申请日：2016-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Sreenath Potty Narayanan

IPC: H04W52/02

Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

公开(公告)号：US20200007365A1

公开(公告)日：2020-01-02

申请号：US16375783

申请日：2019-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jaiganesh Balakrishnan

IPC: H04L27/20 ,  H04L27/22 ,  H04B1/40

Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.