公开(公告)号：US20200266145A1

公开(公告)日：2020-08-20

申请号：US16866255

申请日：2020-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Merle Emerson ,  Benjamin Stassen Cook

IPC: H01L23/525 ,  H01L23/64 ,  H01L21/288 ,  H01L21/78 ,  H01L21/66 ,  H01L49/02

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

公开(公告)号：US10727161B2

公开(公告)日：2020-07-28

申请号：US16055395

申请日：2018-08-06

Applicant: Texas Instruments Incorporated

Inventor： Peter Smeys ,  Ting-Ta Yen ,  Barry Jon Male ,  Paul Merle Emerson

IPC: H01L23/433 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

公开(公告)号：US11302611B2

公开(公告)日：2022-04-12

申请号：US16202925

申请日：2018-11-28

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Paul Merle Emerson ,  Sandeep Shylaja Krishnan

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

公开(公告)号：US10727116B2

公开(公告)日：2020-07-28

申请号：US16048821

申请日：2018-07-30

Applicant: Texas Instruments Incorporated

Inventor： Paul Merle Emerson ,  Benjamin Stassen Cook

IPC: H01L21/768 ,  H01L27/02 ,  H01L21/66 ,  H01L21/78 ,  H01L23/522

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

公开(公告)号：US20200043828A1

公开(公告)日：2020-02-06

申请号：US16055395

申请日：2018-08-06

Applicant: Texas Instruments Incorporated

Inventor： Peter Smeys ,  Ting-Ta Yen ,  Barry Jon Male ,  Paul Merle Emerson

IPC: H01L23/433 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

公开(公告)号：US20200035599A1

公开(公告)日：2020-01-30

申请号：US16048774

申请日：2018-07-30

Applicant: Texas Instruments Incorporated

Inventor： Paul Merle Emerson ,  Benjamin Stassen Cook

IPC: H01L23/525 ,  H01L49/02 ,  H01L23/64 ,  H01L21/78 ,  H01L21/288 ,  H01L21/66

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

公开(公告)号：US20140285925A1

公开(公告)日：2014-09-25

申请号：US13849102

申请日：2013-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajarshi Mukhopadhyay ,  Paul Merle Emerson

IPC: G05F3/02

CPC classification number: H02M3/156 ,  H02M2003/1566

Abstract: A driver circuit includes a first current source configured to sink part of the current from a power supply through a load and a second current source configured to sink part of the current from the power supply to a return path, bypassing the load, so that the current through the load is the difference between the current from the power supply and the current through the second current source.

Abstract translation: 驱动器电路包括被配置为通过负载从电源中吸收电流的一部分的第一电流源和被配置为将部分电流从电源吸收到绕过负载的返回路径的第二电流源， 通过负载的电流是来自电源的电流与通过第二电流源的电流之间的差。