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公开(公告)号：US12237247B2
公开(公告)日：2025-02-25
申请号：US18527457
申请日：2023-12-04
Applicant: Texas Instruments Incorporated
Inventor： Barry Jon Male , Paul Merle Emerson , Sandeep Shylaja Krishnan
IPC: H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.
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公开(公告)号：US12176255B2
公开(公告)日：2024-12-24
申请号：US17589405
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: In some examples, a device comprises a ceramic substrate having a cavity, a die pad in the cavity, and a semiconductor die in the cavity and having a first segment coupled to the die pad and a second segment cantilevered over a floor of the cavity. The device also includes a first conductive member in the cavity, the first conductive member coupled to a second conductive member exposed to an exterior of the ceramic substrate. The device also includes a bond wire coupled to a device side of the semiconductor die and to the first conductive member.
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公开(公告)号：US20220208657A1
公开(公告)日：2022-06-30
申请号：US17698855
申请日：2022-03-18
Applicant: Texas Instruments Incorporated
Inventor： Barry Jon Male , Paul Merle Emerson , Sandeep Shylaja Krishnan
IPC: H01L23/495 , H01L23/00 , H01L21/56 , H01L23/31
Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.
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公开(公告)号：US11837529B2
公开(公告)日：2023-12-05
申请号：US17698855
申请日：2022-03-18
Applicant: Texas Instruments Incorporated
Inventor： Barry Jon Male , Paul Merle Emerson , Sandeep Shylaja Krishnan
IPC: H01L23/495 , H01L23/00 , H01L21/56 , H01L23/31
CPC classification number: H01L23/49513 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/4952 , H01L23/49548 , H01L24/09 , H01L24/17 , H01L24/32 , H01L24/49 , H01L24/73 , H01L2924/1304 , H01L2924/141
Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.
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公开(公告)号：US20140292354A1
公开(公告)日：2014-10-02
申请号：US13851484
申请日：2013-03-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Baher S. Haroun , Rajarshi Mukhopadhyay , Paul Merle Emerson
Abstract: A capacitive sensor has at least first and second conductive areas so that a first capacitance is formed between the first conductive area and a surface, and a second capacitance is formed between the second conductive area and the surface, and the ratio of the first capacitance to the second capacitance has a predetermined value only when the sensor is at a predetermined distance from the surface.
Abstract translation: 电容传感器具有至少第一和第二导电区域，使得在第一导电区域和表面之间形成第一电容，并且在第二导电区域和表面之间形成第二电容，并且将第一电容与第 只有当传感器距离表面处于预定距离时，第二电容具有预定值。
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Patent Agency Ranking
公开(公告)号：US11664273B2
公开(公告)日：2023-05-30
申请号：US16939383
申请日：2020-07-27
Applicant: Texas Instruments Incorporated
Inventor： Paul Merle Emerson , Benjamin Stassen Cook
IPC: H01L21/68 , H01L27/02 , H01L21/66 , H01L23/522 , H01L21/78 , H01L21/768
CPC classification number: H01L21/76838 , H01L21/76801 , H01L21/78 , H01L22/12 , H01L22/14 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L27/0207
Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.
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公开(公告)号：US11538767B2
公开(公告)日：2022-12-27
申请号：US15946868
申请日：2018-04-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Barry Jon Male , Paul Merle Emerson , Kurt Peter Wachtler
IPC: H01L23/31 , H01L23/00 , H01L23/34 , H01L23/495 , H01L23/29 , H01L23/057
Abstract: An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.
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公开(公告)号：US11270939B2
公开(公告)日：2022-03-08
申请号：US16866255
申请日：2020-05-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Paul Merle Emerson , Benjamin Stassen Cook
IPC: H01L23/525 , H01L49/02 , H01L21/66 , H01L21/288 , H01L23/64 , H01L21/78
Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.
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公开(公告)号：US20200035550A1
公开(公告)日：2020-01-30
申请号：US16048821
申请日：2018-07-30
Applicant: Texas Instruments Incorporated
Inventor： Paul Merle Emerson , Benjamin Stassen Cook
IPC: H01L21/768 , H01L27/02 , H01L21/66 , H01L21/78 , H01L23/522
Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.
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公开(公告)号：US20240096761A1
公开(公告)日：2024-03-21
申请号：US18527457
申请日：2023-12-04
Applicant: Texas Instruments Incorporated
Inventor： Barry Jon Male , Paul Merle Emerson , Sandeep Shylaja Krishnan
IPC: H01L23/495 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49513 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/4952 , H01L23/49548 , H01L24/09 , H01L24/17 , H01L24/32 , H01L24/49 , H01L24/73 , H01L2924/1304 , H01L2924/141
Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.
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