公开(公告)号：US10677903B2

公开(公告)日：2020-06-09

申请号：US15367982

申请日：2016-12-02

Applicant: Texas Instruments Incorporated

Inventor： Ravikumar Pattipaka ,  Raja Sekhar Kanakamedala ,  Aravind Miriyala ,  Vajeed Nimran P A ,  Sandeep Kesrimal Oswal

IPC: G01S7/52 ,  A61B8/00 ,  A61B8/08

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

公开(公告)号：US10573292B2

公开(公告)日：2020-02-25

申请号：US15782945

申请日：2017-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ravikumar Pattipaka ,  Vajeed Nimran ,  Sandeep Oswal

IPC: G10K11/34 ,  A61B8/00 ,  G01S15/89 ,  A61B8/08 ,  G01S7/52

Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.

公开(公告)号：US10319362B2

公开(公告)日：2019-06-11

申请号：US15793537

申请日：2017-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ravikumar Pattipaka ,  Raja Sekhar Kanakamedala ,  Aravind Miriyala ,  Sandeep Kesrimal Oswal

IPC: G10K11/34 ,  H03K17/687 ,  H03K19/003 ,  H03K3/356 ,  G10K11/04 ,  G06F1/3203 ,  H03K17/08 ,  G11C11/413 ,  H03K19/0185 ,  B06B1/02 ,  H03K17/56

Abstract: The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.