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公开(公告)号：US11831283B2
公开(公告)日：2023-11-28
申请号：US17210251
申请日：2021-03-23
Applicant: Texas Instruments Incorporated
Inventor： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
CPC classification number: H03F1/56 , H03F3/45475 , G01S7/52033 , H03F2203/45134 , H03F2203/45151 , H03F2203/45528 , H03F2203/45591 , H03G1/0035 , H03G3/301 , H03G3/3005
Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
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公开(公告)号：US11540384B2
公开(公告)日：2022-12-27
申请号：US17014143
申请日：2020-09-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shabbir Amjhera Wala , Xiaochen Xu , Dijeesh K , Abhishek Vishwa , Shriram Devi , Aatish Chandak , Sanjay Dixit , Elisa Maddalena Granata , Jun Shen , Sandeep Oswal
Abstract: An apparatus comprises a transceiver (Tx/Rx) printed circuit board (PCB) with a top surface and a bottom surface and a power supply PCB. The Tx/Rx PCB includes two transmitter devices, each comprising a number N of channels. A first transmitter device is arranged on the bottom surface and a second transmitter device is arranged on the top surface over the first transmitter device. One or more pins of the second transmitter device are shorted with one or more pins of the first transmitter device with the same function. An analog front end (AFE) device comprising N input channels is arranged on the top surface of the Tx/Rx PCB, and a digital signal processor is coupled to the AFE device. The power supply PCB comprises a power supply module configured to provide a plurality of supply voltages to the Tx/Rx PCB and the power supply PCB.
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公开(公告)号：US11063793B1
公开(公告)日：2021-07-13
申请号：US16876308
申请日：2020-05-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ani Xavier , Jagannathan Venkataraman , Sandeep Oswal
Abstract: An equalization circuit includes a feed-forward equalization (FFE) circuit and a decision feedback equalization (DFE) circuit. The FFE circuit includes a first FFE tap, a second FFE tap coupled to the first FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes an input and a DFE tap. The input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.
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公开(公告)号：US11901864B1
公开(公告)日：2024-02-13
申请号：US18088951
申请日：2022-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sravana Kumar Goli , Nagesh Surendranath , Saugata Datta , Sandeep Oswal
CPC classification number: H03B5/1243 , G01J1/42 , G01S17/894 , H03K5/24 , H03L7/0812 , H03M7/12
Abstract: A circuit includes an amplifier having an input and an output. A voltage comparator has an input and first and second outputs. The input of the voltage comparator is coupled to the output of the amplifier. A variable capacitor circuit is coupled between the input and the output of the amplifier and is coupled to the first output of the voltage comparator. A charge dump circuit has an input and an output. The input of the charge dump circuit is coupled to the second output of the voltage comparator. The output of the charge dump circuit is coupled to the input of the amplifier.
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5.发明申请公开(公告)号：US20200177288A1
公开(公告)日：2020-06-04
申请号：US16697236
申请日：2019-11-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Jaiganesh Balakrishnan , Francesco Dantoni
Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.
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Patent Agency Ranking
公开(公告)号：US20250007484A1
公开(公告)日：2025-01-02
申请号：US18217325
申请日：2023-06-30
Applicant: Texas Instruments Incorporated
Inventor： Raja Sekhar , Prashuk Jain , Sandeep Oswal , Ravikumar Pattipaka
Abstract: Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.
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7.发明授权公开(公告)号：US12095431B2
公开(公告)日：2024-09-17
申请号：US17362443
申请日：2021-06-29
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Oswal , Raja Reddy Patukuri , Aravind Miriyala , Anand Hariraj Udupa , Hari Babu Tippana , Aatish Chandak
CPC classification number: H03F3/45475 , A61B5/308 , H03F2200/165
Abstract: An ECG signal acquisition system includes a first amplifier which has a non-inverting input adapted to be coupled to a first differential input, an inverting input adapted to be coupled to a second differential input, and an output. The system includes first and second biasing resistors coupled between the non-inverting and inverting inputs of the first amplifier. The system includes an average estimation circuit which has a first input coupled to the non-inverting input of the first amplifier and a second input coupled to the inverting input of the first amplifier. The system includes a driver amplifier which has an inverting input coupled to the output of the average estimation circuit, a non-inverting input coupled to receive a reference common-mode voltage, and an output. The system includes a low-pass filter coupled between the output of the driver amplifier and the biasing resistors.
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公开(公告)号：US20210003523A1
公开(公告)日：2021-01-07
申请号：US16852736
申请日：2020-04-20
Applicant: Texas Instruments Incorporated
Inventor： Aatish Chandak , Raja Reddy Patukuri , Aravind Miriyala , Sandeep Oswal
Abstract: The disclosure provides a measurement circuit. The measurement circuit includes a control engine. An excitation source is coupled to the control engine. A first set of electrodes and a second set of electrodes are coupled to the excitation source and receive current from the excitation source. The control engine operates the excitation source in a first mode and a second mode. The control engine, in the first mode, measures a parasitic impedance associated with the first and the second set of electrodes, and the control engine, in the second mode, measures an impedance of the first and the second set of electrodes and of an external object.
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公开(公告)号：US10573292B2
公开(公告)日：2020-02-25
申请号：US15782945
申请日：2017-10-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ravikumar Pattipaka , Vajeed Nimran , Sandeep Oswal
Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.
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公开(公告)号：US20150280662A1
公开(公告)日：2015-10-01
申请号：US14637146
申请日：2015-03-03
Applicant: Texas Instruments Incorporated
Inventor： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
CPC classification number: H03F1/56 , G01S7/52033 , H03F3/45475 , H03F2203/45134 , H03F2203/45151 , H03F2203/45528 , H03F2203/45591 , H03G1/0035 , H03G3/3005 , H03G3/301
Abstract: The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.
Abstract translation: 本公开提供了时间增益补偿（TGC）电路。 TGC电路包括阻抗网络。 差分放大器耦合到阻抗网络。 差分放大器包括第一输入端口，第二输入端口，第一输出端口和第二输出端口。 第一反馈电阻耦合在第一输入端口和第一输出端口之间。 第二反馈电阻耦合在第二输入端口和第二输出端口之间。 当TGC电路的增益从最大值变为最小值时，阻抗网络向差分放大器提供固定阻抗。
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