Instruction methods for performing data formatting while moving data
between memory and a vector register file
    11.
    发明授权
    Instruction methods for performing data formatting while moving data between memory and a vector register file 失效
    在存储器和向量寄存器文件之间移动数据的同时执行数据格式化的指令方法

    公开(公告)号:US5812147A

    公开(公告)日:1998-09-22

    申请号:US716972

    申请日:1996-09-20

    IPC分类号: G06F9/312 G06F9/315 G06F13/00

    摘要: Instruction methods for moving data between memory and a vector register file while performing data formatting. The methods are processed by a processor having a vector register file and a memory unit. The methods are useful in the graphics art because they allow more efficient movement and processing of raster formatted graphics data. The vector register file has a number of vector registers (e.g., 32) that each contain multi-bits of storage (e.g., 128 bits). In one class of instructions, eight byte locations within memory are simultaneously loaded into eight separate 16 bit locations within a register of the register file. The data can be integer or fraction and signed or unsigned. The data can also be stored from the register file back to memory. In a second class of instructions, alternate locations of a memory qaudword are selected and simultaneously loaded in the register file. In a third class, data is obtained across a word boundary by a first instruction that obtains a first part and a second instruction that obtains the remainder part crossing the boundary. In a last class of instruction transfers, a block (e.g., 8 16-bit.times.8 16-bit) of data is loaded from memory, stored in the register file and stored back into memory causing a transposition of the data block (16 cycles). A block (e.g., 8 16-bit.times.8 16-bit) of data is stored from the register file to memory, and loaded back into the register file causing a transposition of the data block (16 cycles).

    摘要翻译: 在执行数据格式化时,用于在存储器和矢量寄存器文件之间移动数据的指令方法。 该方法由具有向量寄存器文件和存储单元的处理器处理。 这些方法在图形艺术中是有用的,因为它们允许更有效地移动和处理光栅格式的图形数据。 向量寄存器文件具有多个向量寄存器(例如,32),每个向量寄存器包含多位存储(例如,128位)。 在一类指令中,存储器中的八个字节位置被同时加载到寄存器文件的寄存器内的八个单独的16位位置。 数据可以是整数或分数,有符号或无符号。 数据也可以从寄存器文件存储回存储器。 在第二类指令中,选择存储器字典的替代位置并同时加载到寄存器文件中。 在第三类中,通过获得获得跨越边界的剩余部分的第一部分和第二指令的第一指令跨字边界获得数据。 在最后一类指令传输中,将一个数据块(例如8位16位×16位)从存储器加载到存储器中,并存储在存储器中,导致数据块的转置(16个周期)。 数据块(例如8位16位×16位)从寄存器文件存储到存储器,并加载到寄存器文件中,导致数据块的转置(16个周期)。

    System, method and article of manufacture for a programmable processing model with instruction set
    13.
    发明授权
    System, method and article of manufacture for a programmable processing model with instruction set 有权
    具有指令集的可编程处理模型的系统,方法和制造

    公开(公告)号:US08259122B1

    公开(公告)日:2012-09-04

    申请号:US11942577

    申请日:2007-11-19

    IPC分类号: G09G5/00 G06T1/00

    CPC分类号: G06T15/005 G06T15/503

    摘要: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

    摘要翻译: 提供了一种用于计算机图形管线中的可编程处理的系统,方法和制造物品。 最初,从源缓冲区接收数据。 此后,对数据执行可编程操作以产生输出。 操作是可编程的,因为用户可以利用来自预定指令集的指令来产生它们。 这样的输出被存储在寄存器中。 在运行期间,存储在寄存器中的输出用于对数据执行可编程操作。

    Mapping memory partitions to virtual memory pages
    14.
    发明授权
    Mapping memory partitions to virtual memory pages 有权
    将内存分区映射到虚拟内存页面

    公开(公告)号:US07620793B1

    公开(公告)日:2009-11-17

    申请号:US11467679

    申请日:2006-08-28

    摘要: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

    摘要翻译: 使用非二功能虚拟内存页大小寻址内存的系统和方法通过在渲染过程中分配图形数据进行高效访问来提高图形内存带宽。 可以为每个虚拟存储器页面选择各种分段步长,以修改映射到每个物理存储器分区的顺序地址的数量并改变交织粒度。 寻址方案允许修改每个虚拟存储器页面的存储体交织模式以减少存储体冲突并提高存储器带宽利用率。 寻址方案还允许修改每个虚拟存储器页面的分区交织模式以分布多个分区之间的访问并提高存储器带宽利用率。

    VIRTUAL ARCHITECTURE AND INSTRUCTION SET FOR PARALLEL THREAD COMPUTING
    15.
    发明申请
    VIRTUAL ARCHITECTURE AND INSTRUCTION SET FOR PARALLEL THREAD COMPUTING 有权
    虚拟架构和平行线程计算的指令集

    公开(公告)号:US20080184211A1

    公开(公告)日:2008-07-31

    申请号:US11627892

    申请日:2007-01-26

    IPC分类号: G06F9/45

    CPC分类号: G06F8/456

    摘要: A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.

    摘要翻译: 虚拟架构和指令集支持显式并行线程计算。 虚拟架构定义了支持多个虚拟线程的并行执行的虚拟处理器,该多个虚拟线程具有不同虚拟线程之间的多级数据共享和协调(例如,同步),以及控制虚拟处理器的虚拟执行驱动器。 用于虚拟处理器的虚拟指令集架构用于定义虚拟线程的行为,并且包括与并行线程行为相关的指令,例如数据共享和同步。 使用虚拟平台,程序员可以开发虚拟线程同时执行以处理数据的应用程序; 虚拟翻译器和驱动程序将应用程序代码调整到要执行的特定硬件,对程序员是透明的。

    Neighbor and edge indexing
    16.
    发明授权
    Neighbor and edge indexing 有权
    邻居和边缘索引

    公开(公告)号:US07324105B1

    公开(公告)日:2008-01-29

    申请号:US10727679

    申请日:2003-12-04

    IPC分类号: G06T17/00 G06T17/20

    CPC分类号: G06T17/20

    摘要: Method and apparatus for neighbor and edge indexing is described. A vertex is identified and assigned a reference. One-ring neighbor vertices of the vertex are identified. The reference is assigned to each of the one-ring neighbor vertices identified. An index to one of the one-ring neighbor vertices is assigned. The index is successively incremented to provide indices for each of the one-ring neighbor vertices remaining. Edge indexing follows as described above, with the vertex and its one-ring neighbors defining end points of edges. Additionally, offset indexing is described, and may be used for a consistent order of computation.

    摘要翻译: 描述了用于邻居和边缘索引的方法和装置。 一个顶点被识别并分配一个参考。 识别顶点的单环邻接顶点。 引用被分配给所识别的每个单环邻居顶点。 分配一个环形邻居顶点之一的索引。 索引依次递增,为剩下的每一环邻近顶点提供索引。 边缘索引如上所述,其中顶点及其单环邻居定义边缘的终点。 另外,描述了偏移索引,并且可以用于一致的计算顺序。

    Primitive extension
    17.
    发明授权
    Primitive extension 有权
    原始延伸

    公开(公告)号:US07196703B1

    公开(公告)日:2007-03-27

    申请号:US10728047

    申请日:2003-12-04

    CPC分类号: G06T17/20

    摘要: Method and apparatus for generating a primitive extension defining a generalized primitive is described. The primitive extension defines the connectivity and vertices used to specify a collection of connected primitives, such as a strip-type or fan-type generalized primitive. A generalized primitive includes a number of vertices where some of the vertices are shared with neighboring primitives. The primitive extension includes an originating primitive, vertex data, and connectivity information. The primitive extension provides a general interface for describing a variety of connected primitives.

    摘要翻译: 描述了用于生成定义广义基元的原始扩展的方法和装置。 原始扩展定义了用于指定连接原语集合的连接性和顶点,例如条带类型或扇形广义原语。 广义原语包括一些顶点,其中一些顶点与相邻基元共享。 原始扩展包括始发原语,顶点数据和连接性信息。 原始扩展提供了用于描述各种连接的原语的通用接口。

    User programmable primitive engine
    18.
    发明授权
    User programmable primitive engine 有权
    用户可编程原始引擎

    公开(公告)号:US06940515B1

    公开(公告)日:2005-09-06

    申请号:US10727814

    申请日:2003-12-03

    IPC分类号: G06T1/00

    CPC分类号: G06T1/20

    摘要: A fixed function engine and method are described for processing a set of primitive commands. One embodiment of the fixed function engine includes a means for receiving one or more primitive commands, where each such primitive command includes information for processing vertex data using a user-developed program or subroutine. The fixed function engine also includes a means for determining a set of related primitive commands from the received primitive commands and a means for identifying a first primitive command to process from that set. In addition, the fixed function engine includes a means for transmitting a first program command, which is related to the first primitive command, to a processing engine for processing.

    摘要翻译: 描述了用于处理一组原始命令的固定功能引擎和方法。 固定功能引擎的一个实施例包括用于接收一个或多个原始命令的装置,其中每个这样的原始命令包括用于使用用户开发的程序或子程序来处理顶点数据的信息。 固定功能引擎还包括用于从接收到的原语命令确定一组相关原语命令的装置和用于识别从该组处理的第一原语命令的装置。 此外,固定功能引擎包括用于将与第一原语命令相关的第一程序命令发送到用于处理的处理引擎的装置。

    Direct memory access apparatus for transferring a block of data having
discontinous addresses using an address calculating circuit
    20.
    发明授权
    Direct memory access apparatus for transferring a block of data having discontinous addresses using an address calculating circuit 失效
    用于使用地址计算电路传送具有不连续地址的数据块的直接存储器存取装置

    公开(公告)号:US06108722A

    公开(公告)日:2000-08-22

    申请号:US713602

    申请日:1996-09-13

    IPC分类号: G06F13/28 G06F13/14

    CPC分类号: G06F13/28

    摘要: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete. The number of transactions carried out is also monitored to determine when a DMA transfer is complete.

    摘要翻译: 提供了具有多个事务的dma传送模式的方法和装置。 本发明生成一组用于DMA传输的事务条目,每个事务条目包含与事务的地址和命令指令相关的信息。 交易条目存储在地址/ cmd-output-FIFO中。 本发明协商用于控制系统总线。 在获得对总线的控制之后,与系统总线相关的命令和地址与每个事务相关。 如果事务是读取操作,则从系统总线接收的数据首先被存储在FIFO数据中,然后再发送到所需的目的地。 如果事务是写入操作,则要被传送的数据首先存储在数据输出FIFO中,然后及时放置在系统总线上以传送到所需目的地。 在这两种情况下,监视传输的数据字数,以确定交易何时完成。 还监控执行的事务数,以确定DMA传输何时完成。