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1.发明授权Direct memory access apparatus for transferring a block of data having discontinous addresses using an address calculating circuit 失效用于使用地址计算电路传送具有不连续地址的数据块的直接存储器存取装置
公开(公告)号：US06108722A
公开(公告)日：2000-08-22
申请号：US713602
申请日：1996-09-13
申请人： Mark W. Troeller , Michael L. Fuccio , Linda S. Gardner , Henry P. Moreton , Michael J. K. Nielsen
发明人： Mark W. Troeller , Michael L. Fuccio , Linda S. Gardner , Henry P. Moreton , Michael J. K. Nielsen
CPC分类号： G06F13/28
摘要： A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete. The number of transactions carried out is also monitored to determine when a DMA transfer is complete.
摘要翻译： 提供了具有多个事务的dma传送模式的方法和装置。 本发明生成一组用于DMA传输的事务条目，每个事务条目包含与事务的地址和命令指令相关的信息。 交易条目存储在地址/ cmd-output-FIFO中。 本发明协商用于控制系统总线。 在获得对总线的控制之后，与系统总线相关的命令和地址与每个事务相关。 如果事务是读取操作，则从系统总线接收的数据首先被存储在FIFO数据中，然后再发送到所需的目的地。 如果事务是写入操作，则要被传送的数据首先存储在数据输出FIFO中，然后及时放置在系统总线上以传送到所需目的地。 在这两种情况下，监视传输的数据字数，以确定交易何时完成。 还监控执行的事务数，以确定DMA传输何时完成。
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公开(公告)号：US6078515A
公开(公告)日：2000-06-20
申请号：US196624
申请日：1998-11-18
摘要： A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
摘要翻译： 一种存储器系统，其包括存储器控制器和通过多个总线向存储器组件组提供地址和控制信号的存储器模块。 在一个实施例中，每个存储器模块耦合到地址/控制总线。 使用多个地址/控制总线提供必要的带宽，以便允许快速访问和控制存储器组件。 存储器组件被分组成存储器组件的组，每个存储体包括三个存储器组件。 存储器模块在给定的存储器模块上配置有一个，两个，四个或更多组存储器组件。 在一个实施例中，存储器系统包括使用SDRAM存储器组件的六个48位存储器模块。 六个存储器模块用于一组以形成288位存储器字。 当使用16 Mbit或64 Mbit内存组件时，此配置可提供从32兆字节到2千兆字节的内存配置范围。
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公开(公告)号：US5870325A
公开(公告)日：1999-02-09
申请号：US60451
申请日：1998-04-14
摘要： A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.
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