公开(公告)号：US5812147A

公开(公告)日：1998-09-22

申请号：US716972

申请日：1996-09-20

申请人： Timothy J. Van Hook ,  Henry P. Moreton ,  Michael L. Fuccio ,  Robert W. Pryor, Jr. ,  Charles F. Tuffli, III

发明人： Timothy J. Van Hook ,  Henry P. Moreton ,  Michael L. Fuccio ,  Robert W. Pryor, Jr. ,  Charles F. Tuffli, III

IPC分类号： G06F9/312 ,  G06F9/315 ,  G06F13/00

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/3816

摘要： Instruction methods for moving data between memory and a vector register file while performing data formatting. The methods are processed by a processor having a vector register file and a memory unit. The methods are useful in the graphics art because they allow more efficient movement and processing of raster formatted graphics data. The vector register file has a number of vector registers (e.g., 32) that each contain multi-bits of storage (e.g., 128 bits). In one class of instructions, eight byte locations within memory are simultaneously loaded into eight separate 16 bit locations within a register of the register file. The data can be integer or fraction and signed or unsigned. The data can also be stored from the register file back to memory. In a second class of instructions, alternate locations of a memory qaudword are selected and simultaneously loaded in the register file. In a third class, data is obtained across a word boundary by a first instruction that obtains a first part and a second instruction that obtains the remainder part crossing the boundary. In a last class of instruction transfers, a block (e.g., 8 16-bit.times.8 16-bit) of data is loaded from memory, stored in the register file and stored back into memory causing a transposition of the data block (16 cycles). A block (e.g., 8 16-bit.times.8 16-bit) of data is stored from the register file to memory, and loaded back into the register file causing a transposition of the data block (16 cycles).

摘要翻译： 在执行数据格式化时，用于在存储器和矢量寄存器文件之间移动数据的指令方法。 该方法由具有向量寄存器文件和存储单元的处理器处理。 这些方法在图形艺术中是有用的，因为它们允许更有效地移动和处理光栅格式的图形数据。 向量寄存器文件具有多个向量寄存器（例如，32），每个向量寄存器包含多位存储（例如，128位）。 在一类指令中，存储器中的八个字节位置被同时加载到寄存器文件的寄存器内的八个单独的16位位置。 数据可以是整数或分数，有符号或无符号。 数据也可以从寄存器文件存储回存储器。 在第二类指令中，选择存储器字典的替代位置并同时加载到寄存器文件中。 在第三类中，通过获得获得跨越边界的剩余部分的第一部分和第二指令的第一指令跨字边界获得数据。 在最后一类指令传输中，将一个数据块（例如8位16位×16位）从存储器加载到存储器中，并存储在存储器中，导致数据块的转置（16个周期）。 数据块（例如8位16位×16位）从寄存器文件存储到存储器，并加载到寄存器文件中，导致数据块的转置（16个周期）。

公开(公告)号：US06862278B1

公开(公告)日：2005-03-01

申请号：US09099742

申请日：1998-06-18

申请人： Luke Y. Chang ,  Michael L. Fuccio ,  John C. Liu ,  Gordon Max Elder

发明人： Luke Y. Chang ,  Michael L. Fuccio ,  John C. Liu ,  Gordon Max Elder

IPC分类号： H04J3/04 ,  H04L12/28 ,  H04L12/56 ,  H04N7/26 ,  H04N7/30

CPC分类号： H04N19/436 ,  H04N19/176 ,  H04N19/186 ,  H04N19/60

摘要： A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to recover the bitstream.

摘要翻译： 公开了用于比特流的并行压缩和解压缩的系统和方法。 为了压缩，将比特流分成多个组件，并且使用压缩算法对组件进行编码。 然后从编码的组件构建包。 至少一个分组与每个编码的分量相关联并且包括报头信息和编码数据。 分组被组合成分组化的编码比特流。 对于解压缩，使用报头信息将分组与分组化的编码比特流分离。 然后使用解压缩算法并行解码分组以恢复编码数据。 从恢复的编码数据重建多个分量，并组合以恢复比特流。

公开(公告)号：US5768445A

公开(公告)日：1998-06-16

申请号：US713599

申请日：1996-09-13

申请人： Mark W. Troeller ,  Michael L. Fuccio ,  Henry P. Moreton ,  Bent Hagemark ,  Te-Li Lau

发明人： Mark W. Troeller ,  Michael L. Fuccio ,  Henry P. Moreton ,  Bent Hagemark ,  Te-Li Lau

IPC分类号： H04N7/30 ,  G06T1/20 ,  G06T1/60 ,  H04N1/41 ,  H04N7/26 ,  H04N7/50 ,  G06K9/00

CPC分类号： H04N19/423 ,  H04N19/61

摘要： This relates to a general purpose circuit that maximizes the computing power of a Unix workstation or other computer system for processing image or other data in accordance with a selected one or ones of several alternative compression and decompression algorithms. This dynamically allocates system memory for storage of both compressed and uncompressed data and ensures adequate compression and decompression rates.

摘要翻译： 这涉及一种通用电路，其使得Unix工作站或其他计算机系统的计算能力最大化，用于根据几个替代的压缩和解压缩算法中选择的一个或多个处理图像或其他数据。 这将动态分配系统内存以存储压缩和未压缩数据，并确保足够的压缩和解压缩率。

公开(公告)号：US07180901B2

公开(公告)日：2007-02-20

申请号：US11039771

申请日：2005-01-19

申请人： Luke Y Chang ,  Michael L. Fuccio ,  John C. Liu ,  Gordon Max Elder

发明人： Luke Y Chang ,  Michael L. Fuccio ,  John C. Liu ,  Gordon Max Elder

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04N19/436 ,  H04N19/176 ,  H04N19/186 ,  H04N19/60

摘要： A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.

摘要翻译： 公开了用于比特流的并行压缩和解压缩的系统和方法。 为了压缩，将比特流分成多个组件，并且使用压缩算法对组件进行编码。 然后从编码的组件构建包。 至少一个分组与每个编码的分量相关联并且包括报头信息和编码数据。 分组被组合成分组化的编码比特流。 对于解压缩，使用报头信息将分组与分组化的编码比特流分离。 然后使用解压缩算法并行解码分组以恢复编码数据。 从恢复的编码数据重建多个分量，并组合以恢复比特流。

公开(公告)号：US06108722A

公开(公告)日：2000-08-22

申请号：US713602

申请日：1996-09-13

申请人： Mark W. Troeller ,  Michael L. Fuccio ,  Linda S. Gardner ,  Henry P. Moreton ,  Michael J. K. Nielsen

发明人： Mark W. Troeller ,  Michael L. Fuccio ,  Linda S. Gardner ,  Henry P. Moreton ,  Michael J. K. Nielsen

IPC分类号： G06F13/28 ,  G06F13/14

CPC分类号： G06F13/28

摘要： A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete. The number of transactions carried out is also monitored to determine when a DMA transfer is complete.

摘要翻译： 提供了具有多个事务的dma传送模式的方法和装置。 本发明生成一组用于DMA传输的事务条目，每个事务条目包含与事务的地址和命令指令相关的信息。 交易条目存储在地址/ cmd-output-FIFO中。 本发明协商用于控制系统总线。 在获得对总线的控制之后，与系统总线相关的命令和地址与每个事务相关。 如果事务是读取操作，则从系统总线接收的数据首先被存储在FIFO数据中，然后再发送到所需的目的地。 如果事务是写入操作，则要被传送的数据首先存储在数据输出FIFO中，然后及时放置在系统总线上以传送到所需目的地。 在这两种情况下，监视传输的数据字数，以确定交易何时完成。 还监控执行的事务数，以确定DMA传输何时完成。

公开(公告)号：US5835729A

公开(公告)日：1998-11-10

申请号：US713600

申请日：1996-09-13

申请人： Henry P. Moreton ,  Michael L. Fuccio ,  Mark W. Troeller ,  Charles F. Tuffli, III ,  David K. Barnett

发明人： Henry P. Moreton ,  Michael L. Fuccio ,  Mark W. Troeller ,  Charles F. Tuffli, III ,  David K. Barnett

IPC分类号： H04N9/78 ,  G06F17/00

CPC分类号： H04N9/78

摘要： A method and arrangement for separating interleaved luminance and chrominance color space components data in a single data stream with minimum CPU intervention is provided. In the separating circuit, the separating circuit receives as input a series of graphics/video image data composed of interleaved luminance and chrominance color space components at successive clock cycles. The separating circuit directs selected bytes of the graphics/video image data representing the luminance color space component to a first path wherein luminance component data received at two successive clock cycles are combined. Likewise, selected bytes of the graphics/video image data representing the chrominance color space component are directed to a second path wherein chrominance component data received at two successive clock cycles are combined. Then, the combined luminance and chrominance component data are output alternately. Conversely, a method and arrangement for interleaving luminance and chrominance color space components data in stored separately into a single data stream is also provided.

摘要翻译： 提供了一种用于以最小的CPU干预分离单个数据流中的交错亮度和色度色空间分量数据的方法和装置。 在分离电路中，分离电路在连续的时钟周期作为输入接收由交错亮度和色度色彩空间分量组成的一系列图形/视频图像数据。 分离电路将表示亮度颜色空间分量的图形/视频图像数据的所选字节指向第一路径，其中在两个连续时钟周期接收的亮度分量数据被组合。 类似地，表示色度色彩空间分量的图形/视频图像数据的选定字节被引导到第二路径，其中以两个连续时钟周期接收的色度分量数据被组合。 然后，交替地输出组合的亮度和色度分量数据。 相反地​​，还提供了用于交织存储在单个数据流中的亮度和色度色空间分量数据的方法和装置。